ACT8865
Rev 2, 11-Feb-14
REG3 is above its power-OK threshold when the
reset timer expires, nRSTO is de-asserted, allowing
the microprocessor to begin its boot sequence.
REG4, REG5, REG6 and REG7 can be enabled or
disabled by PWREN after system powers up.
Control Sequences
The ACT8865 features
sequences that are optimized for supporting system
enable and disable sequences of Atmel SAMA5D3
Series: SAMA5D[31/33/34/35/36] and SAM9 series:
a
variety of control
During the boot sequence, the microprocessor must
assert PWRHLD, holding the regulators to ensure
that the system remains powered after nPBIN is
released.
SAM9G[15/25/35/45/46],
SAM9M[10/11], SAM9N[11/12] application
processor.
SAM9X[25/35],
Enabling/Disabling Sequence
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes
before finally set MSTROFF[] bit to 1 to shut the
system down.
A typical enable sequence is initiated whenever
nPBIN is asserted low via 50Kꢀ resistance. The
enable sequence begins by enabling REG3. When
REG3 reaches its power-OK threshold, nRSTO is
asserted low, resetting the microprocessor. When
REG3 reaches its power-OK threshold for 2msꢀ,
REG1 is enabled. When REG3 reaches its power-
OK threshold for 4msꢀ, REG2 is enabled. When
Figure 3:
ACT8865QI303-T Enable/Disable Sequence
ꢀ
ꢀ: Typical value shown, actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting.
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