ACT8847
Rev 5, 15-Nov-12
Table 3:
ACT8847 and S5PC210 Signal Interfacec
ACT8847
PWREN
DIRECTION
SAMSUNG S5PC210
XPWRRGTON
Xi2cSCL[0]
Xi2cSDA[0]
DVS_GPIO1
DVS_GPIO2
DVS_GPIO3
XnRESET
SCL
SDA
VSELR2
GPIO1/VSELR3
GPIO2/VSELR4
nRSTO
nIRQ
XEINT0
nPBSTAT
PWRHLD
XEINT1
XPSHOLD
1: Typical connections shown, actual connections may vary.
shutdown sequence.
Control Signals
Long Press / Power-cycle:
Enable Inputs
If the MR is asserted for more than 4s, ACT8847
commences a power cycle routine in which case all
regulators are turned off and then turned back on. A
status bit, PCSTAT[ ], is set after the power cycle.
The PCSTAT[ ] bit is automatically cleared to 0 after
read.
The ACT8847 features a variety of control inputs,
which are used to enable and disable outputs
depending upon the desired mode of operation.
PWREN, PWRHLD are logic inputs, while nPBIN is
a unique, multi-function input.
nPBIN Multi-Function Input
nPBSTAT Output
The ACT8847 features the nPBIN multi-function
pin, which combines system enable/disable control
with a hardware reset function. Select either of the
two pin functions by asserting this pin, either
through a direct connection to GA, or through a
50kꢀ resistor to GA, as shown in Figure 2.
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage through
a 10kꢀ or greater resistor.
Manual Reset Function
The second major function of the nPBIN input is to
provide a manual-reset input for the processor. To
manually-reset the processor, drive nPBIN directly
to GA through a low impedance (less than 2.5kꢀ).
An internal timer detects the duration of the MR
event:
Figure 2:
nPBIN Input
Short Press / Soft-Reset:
If the MR is asserted for less than 4s, ACT8847
commences a soft-reset operation where nRSTO
immediately asserts low, then remains asserted low
until the nPBIN input is de-asserted and the reset
time-out period expires. A status bit, SRSTAT[ ] , is
set after a soft-reset event. The SRSTAT[ ] bit is
automatically cleared to 0 after read. After Short
Press, set WDSREN[ ] to 1 about 1s after nRSTO
de-assert then clear WDSREN[ ] for properly
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