ACT8847
Rev 5, 15-Nov-12
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
PB
0xC0
[5:2]
-
R
Reserved.
Watchdog Soft-Reset Enable. Set this bit to 1 to enable
watchdog function. When the watchdog timer expires, the PMU
commences a soft-reset routine. This bit is automatically reset to
0 when entering sleep mode.
PB
0xC0
1
WDSREN
R/W
Watchdog Power-Cycle Enable. Set this bit to 1 to enable
watchdog function. When watchdog timer expires, the PMU
commence a power cycle. This bit is automatically reset to 0
when entering sleep mode.
PB
PB
0xC0
0xC1
0
WDPCEN
INTADR
R/W
R
Interrupt Address. It holds the address of the block that triggers
the interrupt. This byte defaults to 0xFF and is automatically set
to 0xFF after being read. Bit 7 is the MSB while Bit 0 is the LSB.
[7:0]
nPBIN Assertion Interrupt Status. The value of this bit is 1 if the
nPBIN Assertion Interrupt is triggered.
PB
PB
0xC2
0xC2
7
6
PBASTAT
PBDSTAT
R
R
nPBIN De-assertion Interrupt Status. The value of this bit is 1 if
the nPBIN De-assertion Interrupt is triggered.
nPBIN Status bit. This bit contains the real-time status of the
nPBIN pin. The value of this bit is 1 if nPBIN is asserted, and is 0
if nPBIN is de-asserted.
PB
0xC2
5
PBASTAT
R
PB
PB
0xC2
0xC3
[4:0]
[7:1]
-
-
R
R
Reserved.
Reserved.
Software Initiated Power Cycle. When this bit is set, the PMU
commences a power cycle after 8ms delay.
PB
PB
PB
0xC3
0xC5
0xC5
0
[7:2]
1
SIPC
-
R/W
R
Reserved.
Power-cycle Flag. The value of this bit is 1 after a power cycle.
This bit is automatically cleared to 0 after read.
PCSTAT
R/W
Soft-reset Flag. The value of this bit is 1 after a soft-reset. This
bit is automatically cleared to 0 after read.
PB
0xC5
0xE3
0xE3
0
SRSTAT
PWM6EN
FRE6
R/W
R/W
R/W
GPIO6
GPIO6
[7]
PWM Function Enable. Set 1 to enable PWM function of GPIO6.
PWM Frequency Selection Bits for GPIO6. See the Table 6 for
code to frequency cross.
[6:4]
Duty Cycle Selection Bits for GPIO6. See the Table 7 for code to
duty cross.
GPIO6
GPIO5
GPIO5
0xE3
0xE4
0xE4
[3:0]
[7]
DUTY6
PWM5EN
FRE5
R/W
R/W
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO5.
PWM Frequency Selection Bits for GPIO5. See the Table 6 for
code to frequency cross.
[6:4]
Duty Cycle Selection Bits for GPIO5. See the Table 7 for code to
duty cross.
GPIO5
GPIO3
GPIO3
0xE4
0xF4
0xF4
[3:0]
[7]
DUTY5
PWM3EN
FRE3
R/W
R/W
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO3.
PWM Frequency Selection Bits for GPIO3. See the Table 6 for
code to frequency cross.
[6:4]
Duty Cycle Selection Bits for GPIO3. See the Table 7 for code to
duty cross.
GPIO3
GPIO4
GPIO4
0xF4
0xF5
0xF5
[3:0]
[7]
DUTY3
PWM4EN
FRE4
R/W
R/W
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO4.
PWM Frequency Selection Bits for GPIO4. See the Table 6 for
code to frequency cross.
[6:4]
Duty Cycle Selection Bits for GPIO4. See the Table 7 for code to
duty cross.
GPIO4
0xF5
[3:0]
DUTY4
R/W
Innovative PowerTM
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