ACT8846
Rev 4, 25-May-16
Figure 4 shows the feedback network necessary to
set the output voltage for REG1 when using the
adjustable output voltage option. Connect the FB1
pin to the output directly to regulate the output
voltage at 1.2V. Select components as follows: Set
OK threshold, typically 7% below the programmed
regulation voltage, that regulator's OK[ ] bit will be 0.
If a DC/DC's nFLTMSK[-] bit is set to 1, the ACT8846
will interrupt the processor if that DC/DC's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
either the regulator is turned off or back in regulation,
and the OK[ ] bit has been read via I2C.
RFB2 = 51kꢀ, then
calculate RFB1 using the
following equation:
VOUT
VFB 1
1
(1)
RFB 1 RFB 2
1
PCB Layout Considerations
where VFB1 is 1.2V. Finally choose CFF using the
following equation:
High switching frequencies and large peak currents
make PC board layout an important part of step-down
DC/DC converter design. A good design minimizes
excessive EMI on the feedback paths and voltage
gradients in the ground plane, both of which can
result in instability or regulation errors.
6
1 10
(2)
C FF
R FB 1
By default, REG2, REG3 and REG4 power up and
regulate to their default output voltages. For REG2,
REG3 and REG4, the output voltage is selectable by
setting corresponding VSELR# pin that when
VSELR# is low, output voltage is programmed by
VSET0[ ] bits, and when VSELR# is high, output
voltage is programmed by VSET1[ ] bits. Also, once
the system is enabled, each regulator's output
voltage may be independently programmed to a
different value. Program the output voltages via the
I2C serial interface by writing to the regulator's
VSET0[ ] register if VSELR# is low or VSET1[ ]
register if VSELR# is high as shown in Table 5.
Step-down DC/DCs exhibit discontinuous input
current, so the input capacitors should be placed as
close as possible to the IC, and avoiding the use of
via if possible. The inductor, input filter capacitor, and
output filter capacitor should be connected as close
together as possible, with short, direct, and wide
traces. The ground nodes for each regulator's power
loop should be connected at a single point in a star-
ground configuration, and this point should be
connected to the backside ground plane with multiple
via. The output node for each regulator should be
connected to its corresponding OUTx pin through the
shortest possible route, while keeping sufficient
distance from switching nodes to prevent noise
injection. Finally, the exposed pad should be directly
connected to the backside ground plane using
multiple via to achieve low electrical and thermal
resistance.
Enable / Disable Control
During normal operation, each buck may be enabled
or disabled via the I2C interface by writing to that
regulator's ON[ ] bit.
OK[ ] and Output Fault Interrupt
Each DC/DC features a power-OK status bit that can
be read by the system microprocessor via the I2C
interface. If an output voltage is lower than the power-
Table 5:
REGx/VSET[ ] Output Voltage Setting
REGx/VSET[5:3]
REGx/VSET[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
0.600
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.250
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
3.600
3.700
3.800
3.900
Innovative PowerTM
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