ACT8796
Rev1, 10-Oct-08
SYSTEM MANAGEMENT
FUNCTIONAL DESCRIPTION
General Description
Manual Enable Due to Asserting nMSTR Low
The ACT8796 offers an array of system manage-
ment functions that allow it to provide optimal per-
formance in a wide range of applications.
System startup is initiated when the user presses
the push-button, asserting nMSTR low. When this
occurs, REG1, REG2, REG3, and REG4 are en-
abled and nRSTO is asserted low to hold the micro-
processor in RESET for 260ms. nRSTO goes high-
Z upon expiration of the reset timer, de-asserting
the processor's reset input and allowing the micro-
processor to initiate its power up sequence. Once
the power-up routine is successfully completed, the
microprocessor must assert PWRHLD so that the
ACT8796 remains enabled after the push-button is
released by the user. Upon completion of the start-
up sequence the processor assumes control of the
power system and all further operation is software-
controlled.
I2C Serial Interface
At the core of the ACT8796's flexible architecture is
an I2C interface that permits optional programming
capability to enhance overall system performance.
To ensure compatibility with a wide range of system
processors, the ACT8796 uses standard I2C com-
mands; I2C write-byte commands are used to pro-
gram the ACT8796, and I2C read-byte commands
are used to read the ACT8796's internal registers.
The ACT8796 always operates as a slave device,
and is addressed using a 7-bit slave address fol-
lowed by an eighth bit, which indicates whether the
transaction is a read-operation or a write-operation,
[1011011x].
Manual Enable Due to Asserting PWRHLD High
The ACT8796 is compatible with applications that
do not utilize its push-button control function, and
may be enabled by simply driving PWRHLD to a
logic-high to enable REG1, REG2, and REG4. In
this case, the signal driving PWRHLD controls en-
able/disable timing, although software-controlled
enable/disable sequences are still supported if the
processor assumes control of the power system
once the startup sequence is completed.
SDA is a bi-directional data line and SCL is a clock
input. The master initiates a transaction by issuing a
START condition, defined by SDA transitioning from
high to low while SCL is high. Data is transferred in
8-bit packets, beginning with the MSB, and is
clocked-in on the rising edge of SCL. Each packet
of data is followed by an Acknowledge (ACK) bit,
used to confirm that the data was transmitted suc-
cessfully.
Shutdown Sequence
For more information regarding the I2C 2-wire serial
interface, go to the NXP website: http://www.nxp.com
Once a successful power-up routine is completed,
the system processor controls the operation of the
power system, including the system shutdown tim-
ing and sequence. When using the application cir-
cuits shown in Figure 2, the nIRQ signal is asserted
when nMSTR is asserted low, providing a simple
means of alerting the system processor when the
user wishes to shut the system down. Asserting
nIRQ interrupts the system processor, initiating an
interrupt service routine in the processor which will
reveal that the user pressed the push-button. The
microprocessor may validate the input, such as by
ensuring that the push-button is asserted for a mini-
mum amount of time, then initiates a software con-
trolled power-down routine, the final step of which is
to de-assert the PWRHLD input, disabling the regu-
lators and shutting the system down.
System Startup and Shutdown
The ACT8796 features a flexible control architec-
ture that supports a variety of software-controlled
enable/disable functions that make it a simple yet
flexible and highly configurable solution. The
ACT8796 is automatically enabled when either of
the following conditions exists:
1) nMSTR is asserted low, or
2) PWRHLD is asserted high.
If either of these conditions is true, the ACT8796
enables REG1, REG2, REG4, and may be REG3
powering up the system processor so that the
startup and shutdown sequences may be controlled
via software. These startup conditions are de-
scribed in detail below.
Innovative PowerTM
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