®
ACT5830
SYSTEM MANAGEMENT
Rev 2, 20-Jan-11
I
2
C INTERFACE ELECTRICAL CHARACTERISTICS
PARAMETER
SCL, SDA Low Input Voltage
SCL, SDA High Input Voltage
SCL, SDA Leakage Current
SDA Low Output Voltage
SCL Clock Period, t
SCL
SDA Data In Setup Time to SCL High, t
SU
SDA Data Out Hold Time after SCL Low, t
HD
SDA Data Low Setup Time to SCL Low, t
ST
SDA Data High Hold Time after Clock High, t
SP
Start Condition
Stop Condition
V
CHG_IN
= 4.2V
I
OL
= 5mA
f
SCL
clock freq = 400kHz
2.5
100
300
100
100
1.4
1
0.3
TEST CONDITIONS
MIN
TYP
MAX
0.4
UNIT
V
V
µA
V
µs
ns
ns
ns
ns
Figure 1:
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2
C Serial Bus Timing
Note: Each session of data transfer is with a start condition, a 7-bits slave address plus a bit to instruct for read or write followed by an
acknowledge bit, a register address byte followed by an acknowledge bit, a data byte followed by an acknowledge bit and a stop condi-
tion. The device address, the register address and the data are all MSB first transferred. Each bit volume is prepared in during the SCL
is low, is latched-in by the rising edge of the SCL. The data byte is accepted and is put effective by the time that the last bit volume is
latched-in.
Innovative Power
TM
ActivePMU
TM
is a trademark of Active-Semi.
I
2
C
TM
is a trademark of NXP.
-9-
www.active-semi.com
Copyright © 2010 Active-Semi, Inc.
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
