ACT412
Rev 1, 30-Oct-13
TYPICAL APPLICATION CONT’D
line frequency, tC is the estimated rectifier
conduction time, CIN is empirically selected to be
2х6.8µF electrolytic capacitors.
Design Example
The design example below gives the procedure for
a DCM fly back converter using an ACT412. Refer
to Application Circuit Figure 2, the design for an
adapter application starts with the following
specification:
The full load system duty cycle is set to be 40% at
low line voltage 85VAC and the circuit efficiency is
estimated to be 75%. Then the average input
current at full load is:
Input Voltage Range
Output Power, PO
90VAC - 265VAC, 50/60Hz
P OUT
_
FL
5W
12V
0.4A
1.8A
0.75
IIN
=
_
FL
V INDC
× η
_
MIN
(5)
(6)
(7)
Output Voltage, VOUTCV
Full Load Current, IOUTFL
CC Current, IOUTMAX
System Efficiency CV, η
5
=
≈ 75 mA
90 × 0 . 75
The input primary peak current at full load:
2 × LI
2 × 75
0.4
N _ FL
The operation for the circuit shown in Figure 1 is as
follows: the rectifier bridge D1-D4 and the capacitor
C1/C2 convert the AC line voltage to DC. This
voltage supplies the primary winding of the
transformer T1 and the startup resistor R7/R8 to
VDD pin of ACT412 and C4. The primary power
current path is formed by the transformer’s primary
winding, the mosfet, and the current sense resistor
R9. The resistors R3, R2, diode D5 and capacitor
C3 create a snubber clamping network that protects
Q1 from voltage spike from the transformer primary
winding leakage inductance. The network
consisting of capacitor C4, diode D6 and resistor
R4 provides a VDD supply voltage for ACT412 from
the auxiliary winding of the transformer. The resistor
R4 is optional, which filters out spikes and noise to
makes VDD more stable. C4 is the decoupling
capacitor of the supply voltage and energy storage
component for startup. During power startup, the
current charges C4 through startup resistor R7/R8
from the rectified high voltage. The diode D8 and
the capacitor C5/C6 rectify filter the output voltage.
The resistor divider consists of R5 and R6
programs the output voltage.
Ippk
=
=
= 375 mA
_ FL
DFL
The primary inductance of the transformer:
VINDC
D FL
_ MIN
Lp
=
Ippk
× fs
_ FL
90 × 0 .4
375 mA × 130 k
=
≈ 0 .74 mH
The primary turns on time at full load:
Ippk
_ FL
TON
= Lp
_ FL
VINDC
_ MIN
(8)
0.74 mH × 375 mA
=
= 3.08 μs
90
The ringing periods from primary inductance with
mosfet Drain-Source capacitor:
TRINGING
= 2π Lp _ MAX CDS _ MAX
_ MAX
(9)
= 2 × 3.14 × 0.73mH × (1 + 7%) ×100PF = 1.76 μs
Design only an half ringing cycle at maximum load
in minimum low line, so secondly reset time:
TRST = TSW -TON _FL - 0.5TRINGING _MAX
Since a bridge rectifier and bulk input capacitors are
used, the resulting minimum and maximum DC
input voltages can be calculated:
(10)
=1 / 130kHz - 3.08μs - 0.5 ×1.76μs = 3.73μs
Base on conservation of energy and transformer
transform identity, the primary to secondary turns
ratio NP/NS:
1
2POUT
(
- tC )
2fL
η × CIN
VINDC _ MIN
=
2VIN2AC _ MIN
VIN
NP
TON
_ MIN
=
×
NS
TRST
VOUT + VD
1
(3)
(4)
(11)
2 × 5 × (
- 3.5ms )
=
2 × 852
-
≈90V
2 × 47
0.75 × 2 × 6.8μF
3.08
90
=
×
= 5.53
3.73 13 + 0.45
VIN ( MAX
=
2 ×VIN ( MAX
The auxiliary to secondary turns ratio NA/NS:
)DC
)AC
=
2 × (265 VAC ) = 375 V
NA
VDD + VD'
18 + 0.45
=
=
= 1.37
(12)
NS VOUT + VD 13 + 0.45
Where ŋ is the estimated circuit efficiency, fL is the
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