Active-Semi
ORDERING INFORMATION
PART NUMBER
ACT4050YH
ACT4050YH-T
TEMPERATURE RANGE
-40°C to 85°C
-40°C to 85°C
PACKAGE
SOP-8/EP
SOP-8/EP
PINS
8
8
ACT4050
Rev 2, 01-Jul-11
PACKING
TUBE
TAPE & REEL
PIN CONFIGURATION
SOP-8/EP
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
EP
NAME
BS
IN
SW
GND
FB
COMP
EN
N/C
EP
DESCRIPTION
Bootstrap. This pin acts as the positive rail for the high-side switch’s gate driver. Connect
a 10nF capacitor between BS and SW.
Input Supply. Bypass this pin to GND with a low ESR capacitor. See
Input Capacitor
in
the
Application Information
section.
Switch Output. Connect this pin to the switching end of the inductor.
Ground.
Feedback Input. The voltage at this pin is regulated to 0.817V. Connect to the resistor
divider between output and ground to set output voltage.
Compensation Pin. See
Stability Compensation
in the
Application Information
section.
Enable Input. When higher than 1.3V, this pin turns the IC on. When lower than 0.9V, this
pin turns the IC off. Output voltage is discharged when the IC is off. When left
unconnected, EN is pulled up to 4.5V typical with a 2µA pull-up current.
Not Connected.
Exposed Pad shown as dashed box. The exposed thermal pad should be connected to
board ground plane and pin 4. The ground plane should include a large exposed copper
pad under the package for thermal dissipation (see package outline). The leads and
exposed pad should be flush with the board, without offset from the board surface.
Innovative Power
TM
-2-
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ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
