ACT361
Rev 8, 14-Nov-12
TYPICAL APPLICATION CONT’D
where η is the estimated circuit efficiency, fL is the
line frequency, tC is the estimated rectifier
conduction time, CIN is empirically selected to be
2 × 4.7µF electrolytic capacitors based on the
3µF/W rule of thumb.
LP
2.3mH
(11)
NP
=
=
= 140
ALE
117 nH / T 2
The number of turns of secondary and auxiliary
windings can be derived accordingly:
NS
NP
1
When the transistor is turned off, the voltage on the
transistor’s collector consists of the input voltage
and the reflected voltage from the transformer’s
secondary winding. There is a ringing on the rising
top edge of the flyback voltage due to the leakage
inductance of the transformer. This ringing is
clamped by a RCD network if it is used. Design this
clamped voltage as 50V below the breakdown of
the NPN transistor. The flyback voltage has to be
considered with selection of the maximum reverse
voltage rating of secondary rectifier diode. If a 40V
Schottky diode is used, then the flyback voltage can
be calculated:
(12)
NS
NA
=
× NP
=
×140 = 10
14
NA
NS
(13)
=
× NS = 2.7 ×10 = 27
The current sense resistance (RCS) determines the
current limit value based on the following equation:
0.9×VCSLIM
IOUTFL +IOUTMAX
0.9×0.396
0.7 +0.9 ×5
RCS
=
=
=1.07R
(
)
×VOUT
(
)
0.69
0.9
η
⎛
⎝
⎞
⎟
⎛
⎞
(14)
system
2.35×40×
⎜
⎜
⎜
⎟
⎟
LP ×FSW
×
⎠
ηxfm
⎝
⎠
Where Fsw is the frequency at CC mode.
VINDCMAX ×(VOUTCV +VDS
VDREV −VOUTCV
)
375 ×(5 + 0.3)
40 ×0.8 − 5
The voltage feedback resistors are selected
according to below equation:
VRO
=
=
= 73.5V
(5)
NA LP
27 2.35
where VDS is the Schottky diode forward voltage,
VDREV is the maximum reverse voltage rating of the
diode and VOUTCV is the output voltage.
RFB1
=
×
× K =
×
×126237 ≈ 53.6k
(15)
NP RCS
140 1.07
Where K is IC constant and K = 126237.
VFB
The maximum duty cycle is set to be 35% at low
line voltage 85VAC and the circuit efficiency is
estimated to be 70%. Then the full load input
current is:
RFB 2
=
RFB1
NA
NS
(VOUTCV +VDS
)
−VFB
(16)
2.20
=
× 53.6 = 9.76k
(5 + 0.3 )× 2.7 − 2.20
VOUTCV ×IOUTPL
5 ×0.7
90 ×70%
(6)
IIN
=
=
= 55.56mA
When selecting the output capacitor, a low ESR
electrolytic capacitor is recommended to minimize
ripple from the current ripple. The approximate
equation for the output capacitance value is given by:
VINDCMIN ×η
The maximum input primary peak current at full
load base on duty of 35%:
2 ×IIN 2 ×55.56
(7)
IOUTCC
0.7
IPK
=
=
= 318mA
COUT
=
=
= 333μF
(17)
D
35%
fSW ×△VRIPPLE 42kHz×50mV
The primary inductance of the transformer:
A 470µF electrolytic capacitor is used to keep the
ripple small.
VINDCMIN × D
IPK × fSW
90 × 35%
318 mA × 42kHz
(8)
LP
=
=
= 2.35 mH
Where fSW is the full load frequency at CV mode.
PCB Layout Guideline
Good PCB layout is critical to have optimal
performance. Decoupling capacitor (C3), current
sense resistor (R7) and feedback resistor (R8/R9)
should be placed close to VDD, CS and FB pins
respectively. There are two main power path loops.
One is formed by C1/C2, primary winding, NPN
transistor and the ACT361. The other is the
secondary winding, rectifier D7 and output
capacitors (C7). Keep these loop areas as small as
possible. Connect high current ground returns, the
input capacitor ground lead, and the ACT361 G pin
to a single point (star ground configuration).
The primary to secondary turns ratio NP/NS:
NP
NS
VRO
74
(9)
=
=
= 14
VOUTCV + VDS
5 + 0.3
The auxiliary to secondary turns ratio NA/NS:
NA VDD +VDA 14.5 +0.7
NS VOUTCV +VDS +VCORD 5 +0.30+0.3
(10)
=
=
= 2.7
Where VDA is the diode forward voltage of the
auxiliary side.
An EE16 transformer gapped core with an effective
inductance ALE of 117nH/T2 is selected. The
number of turns of the primary winding is:
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