Active-Semi
Pulse Modulation
The PFWM Switching Control Logic block operates
in different modes depending on the output load
current level. At light load, the V
VDD
voltage is
around 4.75V. The energy delivered by each
switching cycle (with minimum on time of 500ns) to
the output causes V
VDD
to increase slightly above
4.75V. The FPWM Switching Control Logic block is
able to detect this condition and prevents the IC
from switching until V
VDD
is below 4.75V again. This
results in a pulse-modulation action with fixed pulse
width and varying frequency, and low power
consumption because the switching frequency is
reduced. Typical system standby power
consumption is 0.15W.
Rev 5, 05-Jun-09
ACT30
Short Circuit Hiccup
When the output is short circuited, the ACT30
enters hiccup mode operation. In this condition, the
auxiliary supply voltage collapses. An on-chip
detector compares DRV1 voltage during the off-
time of each cycle to 6.8V. If DRV1 voltage is below
6.8V, the IC will not start the next cycle, causing
both the auxiliary supply voltage and V
VDD
to reduce
further. The circuit enters startup mode when V
VDD
drops below 3.35V. This hiccup behavior continues
until the short circuit is removed. In this behavior,
the effective duty cycle is very low resulting in very
low short circuit current.
To make sure that the IC enters hiccup mode
easily, the transformer should be constructed so
that there is close coupling between secondary and
auxiliary, so that the auxiliary voltage is low when
the output is short-circuited. This can be achieved
with the primary/auxiliary/secondary sequencing
from the bobbin.
Innovative Power
TM
ActiveSwitcher
TM
-6-
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