ACT2823
REV 1, 01-DEC-2016
ꢇ
ꢈꢉꢊ ∗ ꢅ1 ꢆ ꢇꢇꢈꢉꢊꢍ
the VIN pin. Connect the ground side to the PGND
plane.
ꢇ
ꢋꢌꢊ
ꢋꢌꢊ
ꢘꢙꢚꢑ ꢄ ꢁꢏꢐꢑ
∗
ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢖ14ꢗ
ꢒꢓꢔ ∗ ꢎꢛꢜꢝꢝꢂꢞ
5. Use Kevin sense connections from the output current
sense resistor to CSP and CSN pins, and from the
battery charging current sense resistor to BATS and
BATP.
Where IOUT is the load current, VOUT is the 5V output
voltage, VBAT is the battery voltage, FSW is the switching
frequency, and VRIPPLE is the desired ripple voltage.
6. SW node is noisy and should be isolated from other
sensitive circuitry. Make the connection from SW to the
inductor with a short, wide trace for good EMI and low
noise operation.
Charge Current Sense Resistor
Choose a charge current sense resistor so the fast
charge current through it results in a current sense
voltage between 20mV-75mV. Typical resistor values
are 25mΩ to 50mΩ. The traces to the BATP and BATS
pins must be Kelvin sensed to ensure accuracy. In
noisy environments placing a 100nF capacitor between
BATP and BATS will improve noise immunity.
7. The exposed pad is must be connected to the top
layer GND plane. Connect it to the internal and bottom
layer ground planes using thermal vias. PGND and
AGND should be single-point connected to the exposed
pad under the IC.
Output Sense Resistor
8. An RC snubber and external Schottky diode across
SW to PGND can be added as needed for reducing
switching spikes and better EMI performance.
Choose an output current sense resistor so the
maximum load current through it results in a current
sense voltage greater than 10mV. The traces to the
CSP and CSN pins must be Kelvin sensed to ensure
accuracy. The following equation sets the output
current limit
0.066ꢎ
IOUT_CL ꢄꢃꢃ
ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢖ15ꢗ
ꢟꢠꢓ
Where RCS is the current sense resistor between CSN
and CSP.
PCB Board Layout Guidance
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC.
1. Place the BAT decoupling capacitors as close to the
Bat pin as possible. Minimize the loop area between
the BAT pin to the capacitors to the PGND pin. If using
different sized capacitors, place the physically smaller
capacitors closer to the IC to get better high frequency
filtering.
2. Arrange the power components to reduce the overall
AC loop area.
3. Place the VOUT decoupling ceramic capacitors close
to the VOUT pin. Connect the ground side to the PGND
plane.
4. Place the VIN decoupling ceramic capacitors close to
Application Circuit
The following schematic represents a typical application circuit.
Innovative PowerTM
ActiveSwitcherTM is a trademark of Active-Semi.
18
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
