ACT2801/ACT2801B/ACT2801C
Rev 9, 14-Mar-17
PC Board Layout Guidance
When laying out the printed circuit board, the
following checklist should be used to ensure proper
operation of the IC.
size). SW pad is a noisy node switching. It
should be isolated away from the rest of circuit
for good EMI and low noise operation.
1. Arrange the power components to reduce the
AC loop size, VIN pin, Vout pin, SW pin and the
schottky diode.
6. Thermal pad is connected to GND layer through
vias (recommend 4X4 pins and the aperture is
10mil). Ground plane, PGND and AGND is
single point connected under the ACT2801/
ACT2801B/ACT2801C thermal pad through
vias to limited SW area.
2. Place input decoupling ceramic capacitor C3
and R10 as close to VIN pin as possible.
Resistor R10 is added in series with capacitor
C3 to damp the potential LC resonance .
7. From BAT pin to the Battery positive terminal,
need to lay the divided line to ensure the
battery voltage accuracy of sampling.
3. Use copper plane for power GND for best heat
dissipation and noise immunity.
8. RC snubber is recommended to add across SW
to PGND to reduce SW spike below 7V.
2A /20V schottky is added to across VOUT and
SW pins.
A demo board PCB layout example is shown in the
figure 21.
4. Place CSP and CSN capacitor C6 (10nF) close
to CSP and CSN pin as possible, use Kevin
Sense from sense resistor R2 and R2A to CSP
and CSN pins. 22uF decoupling capacitor is
added close to BAT pin.
5. Place the ceramic capacitor C2 and D1 as
close to VOUT and PGND as possible, SW
goes under the C2 (recommend C2 to use 1206
Figure 21.
PCB Layout
Bottom Layer
Top Layer
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