®
ACT2103
Rev 2, 23-May-12
FUNCTIONAL BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
As seen in Function Block Diagram, the ACT2103 is
peak current mode controlled synchronous Buck
converter. The converter operates as follows:
A switching cycle starts when the rising edge of the
Oscillator clock output causes the High-Side Power
Switch to turn on and the Low-Side Power Switch to
turn off. With the SW side of the inductor now
connected to IN, the inductor current ramps up to
store energy in the magnetic field. The inductor
current level is measured by the Current Sense
Amplifier and added to the Oscillator ramp signal. If
the resulting summation is higher than the COMP
voltage, the output of the PWM Comparator goes
high. When this happens or when Oscillator clock
output goes low, the High-Side Power Switch turns
off and the Low-Side Power Switch turns on. The
High-Side Power Switch is driven by logic using
HSB as the positive rail. This pin is charged to VSW
+ 5V when the Low-Side Power Switch turns on.
The COMP voltage is the integration of the error
between FB input and the internal 0.923V
reference. If FB is lower than the reference voltage,
COMP tends to go higher to increase current to the
output to keep the output voltage regulated. The
Oscillator normally switches at 310kHz.
ACT2103 skips pulse automatically and thus
achieve very high light load efficiency. With load
increasing, ACT2103 goes into Discontinuous
Current Mode (DCM) and then Continuous Current
Mode (CCM).
Soft Startup
The ACT2103 builds in internal soft startup
function. The internal FB reference voltage rises to
steady state of 0.923V in 2ms to avoid inrush input
current during startup.
Under Voltage Protection (UVP)
At output short circuit or over current, the FB
voltage is usually pulled low. To protect the IC at
over current and short circuit, the ACT2103 builds
in Under Voltage Protection (UVP) function. When
ACT2103 detects the FB voltage below 80% of the
0.923V reference, it pulls low COMP voltage and
discharges internal soft-start capacitor and goes
into hiccup mode. The IC restarts in 32ms after
going into hiccup mode. If the short circuit or over
current is clear, the IC restarts back to normal
mode. The UVP is disabled for 6ms starting from
startup. If the output is short at startup, the output
voltage never rises to nominal voltage. During the
6ms period of time, the output current is limited by
cycle-by-cycle current limit. With 32ms shutdown
period, the average input and output current at
short circuit is significantly reduced and the IC is
more reliable.
Pulse Skipping Mode
To decrease the power recycling at very light load,
the low-side FET current is sensed to emulate a
diode. When the low-side FET current decreases to
zero, the FET is turned off to avoid negative
inductor current. At no load and very light load,
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