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    OTB25LPLL 参数 Datasheet PDF下载

    OTB25LPLL图片预览
    型号： OTB25LPLL
    PDF下载： 下载PDF文件 查看货源
    内容描述： 超快速的本地和长途线网络 [Ultra-Fast Local and Long-Line Network]
    分类和应用：
    文件页数/大小： 174 页 / 1510 K
    品牌： ACTEL [ Actel Corporation ]
     浏览型号OTB25LPLL的Datasheet PDF文件第162页浏览型号OTB25LPLL的Datasheet PDF文件第163页浏览型号OTB25LPLL的Datasheet PDF文件第164页浏览型号OTB25LPLL的Datasheet PDF文件第165页浏览型号OTB25LPLL的Datasheet PDF文件第167页浏览型号OTB25LPLL的Datasheet PDF文件第168页浏览型号OTB25LPLL的Datasheet PDF文件第169页浏览型号OTB25LPLL的Datasheet PDF文件第170页  
    PLUS  
    ProASIC  
    Flash Family FPGAs  
    Datasheet Information  
    List of Changes  
    The following table lists critical changes that were made in the current version of the document.  
    Previous version  
    Changes in current version (v5.2)  
    Page  
    N/A  
    v5.1  
    MIL-STD-883 was added to the datasheet.  
    V
    and V  
    were changed to V .  
    DDP  
    N/A  
    CC  
    CCI  
    Table 1-9 was updated to include 135°C.  
    page 1-20  
    page 2-6  
    v5.0  
    In the "208-Pin PQFP" table, the following pin numbers have been updated:  
    Pin Number  
    Function  
    I/O / GL2  
    I/O / GL1  
    24  
    30  
    In the "208-Pin CQFP" table, the following pin numbers have been updated:  
    page 2-13  
    Pin Number  
    Function  
    23  
    I/O / GLMX1  
    I/O / GL2  
    24  
    28  
    PPECL1 / Input  
    I/O / GL1  
    30  
    128  
    129  
    134  
    135  
    I/O / GL3  
    PPECL2 / Input  
    I/O / GL4  
    I/O / GLMX2  
    In the "624-Pin CCGA/LGA" table, the following pin numbers have been updated:  
    page 2-82  
    Pin Number  
    M6  
    Function  
    I/O / GL2  
    M7  
    I/O / GLMX1  
    I/O / GLMX2  
    I/O / GL4  
    M19  
    M20  
    N5  
    PPECL1 / Input  
    I/O / GL1  
    N6  
    N20  
    I/O / GL3  
    N21  
    PPECL2 / Input  
    v4.1  
    MIL-STD 883B data will be added into this datasheet after the MIL-STD 883B qualification is  
    complete.  
    Green packaging information in the "Ordering Information" section was updated.  
    The "Temperature Grade Offerings" table was updated for the CG624.  
    The "Ordering Information" section was updated.  
    page ii  
    page iii  
    page ii  
    The "Live at Power-Up" section is new.  
    page 1-3  
    page 1-4  
    page 1-9  
    page 1-9  
    page 1-9  
    page 1-10  
    page 1-13  
    page 1-33  
    Note 2 in Figure 1-4 was updated.  
    The 3.3 V column in Table 1-3 was updated.  
    The "Input/Output Blocks" section was updated.  
    The note was removed from Table 1-4.  
    The "Power-Up Sequencing" section was updated.  
    The first bullet in the "ProASICPLUS Clock Management System" section was updated.  
    The first paragraph in the "Performance Retention" section was updated.  
    v5.2  
    3-1  
    PLUS  
    ProASIC  
    Flash Family FPGAs  
    Previous version  
    Changes in current version (v5.2)  
    Mixed Voltage was removed from Table 1-19.  
    Table 1-20 was updated.  
    Page  
    page 1-35  
    page 1-35  
    Mixed Mode Voltage was removed from Table 1-21 and the Military/MIL-STD-883B column was page 1-36  
    updated.  
    All tables from page 1-42 to page 1-51 were updated.  
    page 1-42 to  
    page 1-51  
    Table 1-48 is new.  
    page 1-53  
    page 1-53  
    page 1-55  
    page 1-59  
    page 1-72  
    Table 1-66  
    page 1-73  
    Figure 1-30 is new.  
    Note 1 in Table 1-50 was updated.  
    The notes in Table 1-54 were updated.  
    A note was added to Figure 1-48.  
    A note was added to Table 1-66.  
    The "TRST Test Reset Input" section was updated in the "Pin Description" section.  
    The "624-Pin CCGA/LGA" section was updated for the APA600 and APA1000. Please review all page 2-81  
    pin data.  
    v4.0  
    v3.5  
    Figure 1-20 was updated.  
    page 1-19  
    page 1-52  
    page 2-69  
    Table 1-46 was updated.  
    The "1152-Pin FBGA" figure was updated.  
    Pin names were changed to more accurately reflect the multiple functions supported by each  
    pin.  
    PLUS  
    PLUS  
    The ProASIC  
    and ProASIC  
    Military/Aerospace datasheets were combined. This document  
    now supports Commercial, Industrial, and Military Temperature devices.  
    Table 1 was updated.  
    page i-i  
    page i-ii  
    page i-ii  
    The "Ordering Information" section was updated.  
    "Plastic Device Resources" table was updated.  
    The Long Term Jitter Peak-to-Peak Max. in the "PLL Electrical Specifications" table was updated. page 1-21  
    The "Calculating Typical Power Dissipation" section was updated.  
    "Performance Retention" section  
    page 1-30  
    page 1-33  
    page 1-34  
    page 1-35  
    page 1-36  
    page 1-38  
    page 1-52  
    page i-iii  
    Table 1-18  
    Table 1-20 was updated.  
    Table 1-21 was updated.  
    Table 1-22 was updated.  
    Table 1-46 was updated.  
    v3.4  
    The "Temperature Grade Offerings" table is new.  
    The "Speed Grade and Temperature Matrix" table is new.  
    The "ProASICPLUS Clock Management System" section was updated.  
    The "Lock Signal" section was updated.  
    page i-iii  
    page 1-13  
    page 1-16  
    page 1-21  
    page 1-22  
    page 1-27  
    page 1-29  
    page 1-65  
    page 1-73  
    The "PLL Electrical Specifications" table was updated.  
    The "User Security" section was updated.  
    The "Design Environment" section was updated.  
    Table 1-15 was updated.  
    The "Asynchronous FIFO Full and Empty Transitions" section was updated.  
    The "AVDD PLL Power Supply" section in the "Pin Description" section was updated.  
    3-2  
    v5.2  
    PLUS  
    ProASIC  
    Flash Family FPGAs  
    Previous version  
    Changes in current version (v5.2)  
    Page  
    v3.3  
    The "144-Pin TQFP" table on page 2-4 was updated. The following pins changed:  
    page 2-4  
    Pin 15 = GLMX1  
    Pin 16 = GL1  
    Pin 21 = GL2  
    Pin 88 = GL3  
    Pin93 = GL4  
    Pin 94 = GLMX2  
    v3.2  
    The "ProASICPLUS Clock Management System" section was updated.  
    Figure 1-14 was updated.  
    page 1-13  
    page 1-14  
    page 1-15  
    page 1-19  
    page 1-21  
    page 1-42  
    page 1-30  
    page 1-33  
    page 1-74  
    Table 1-7 is new.  
    Figure 1-20 was updated.  
    The "PLL Electrical Specifications" section was updated.  
    Figure 1-26 was updated.  
    In the "Calculating Typical Power Dissipation" section, P9 was changed to 7.5 mW.  
    The "Programming, Storage, and Operating Limits" section was updated.  
    The "Recommended Design Practice for VPN/VPP" section was updated.  
    v3.1  
    v3.0  
    The datasheet was updated to include references to guidelines concerning the use of certain  
    PLUS  
    ProASIC  
    I/O standards.  
    In Table 1-2 on page 1-8, the Memory Rows – Bottom coordinates were changed.  
    Figure 1-8 was updated.  
    page 1-8  
    page 1-8  
    page 1-38  
    page 1-44  
    The V Minimum in the Table 1-22 was changed from 0.3 to –0.3.  
    IL  
    In the "Output Buffer Delays" section, the OB25LPLL t  
    Standard changed to 5.3.  
    DHL  
    In the "Sample Macrocell Library Listing" section, the AND2 Standard maximum changed to 0.7 page 1-51  
    and the –F maximum changed to 0.8.  
    v2.0  
    The Table 1 was updated.  
    page i-i  
    The "Ordering Information" section was updated.  
    The "Plastic Device Resources" section was updated.  
    The "ProASICPLUS Architecture" section was updated.  
    Table 1-2 was updated.  
    page i-ii  
    page i-ii  
    page 1-2  
    page 1-8  
    page 1-16  
    page 1-10  
    Table 1-8 is new.  
    Figure 1-11 is new.  
    The Introduction section in the "ProASICPLUS Clock Management System" section was page 1-13  
    updated.  
    The "Physical Implementation" section was updated.  
    page 1-13  
    page 1-13  
    The "Functional Description" on page 1-13 was updated.  
    Figure 1-14 on page 1-14 through Figure 1-20 on page 1-19 were updated.  
    page 1-14 to page  
    1-19  
    The "PLL Electrical Specifications" on page 1-21 was updated.  
    Figure 1-25 on page 1-26 was updated.  
    page 1-21  
    page 1-26  
    page 1-30  
    page 1-34  
    page 1-38  
    page 1-42  
    page 1-44  
    page 1-46  
    page 1-50  
    page 1-51  
    The "Calculating Typical Power Dissipation" on page 1-30 was updated.  
    The ’Nominal Supply Voltages’ section was updated.  
    The Table 1-22 was updated.  
    The "Tristate Buffer Delays" on page 1-42 was updated.  
    The "Output Buffer Delays" on page 1-44 was updated.  
    The"Input Buffer Delays" on page 1-46 was updated.  
    "Global Routing Skew" on page 1-50 was updated.  
    The"Sample Macrocell Library Listing" on page 1-51 was updated.  
    v5.2  
    3-3  
    PLUS  
    ProASIC  
    Flash Family FPGAs  
    Previous version  
    Changes in current version (v5.2)  
    Page  
    page 1-73  
    v2.0 (continued)  
    The "Pin Description" on page 1-73 was updated.  
    The following pins have been changed in the "100-Pin TQFP" table:  
    page 2-1  
    Pin Number  
    Function  
    I/O (GLMX1)  
    GL1  
    NPECL1  
    PPECL1(I/P)  
    GL2  
    Pin Number  
    Function  
    GL3  
    PPECL2 (I/P)  
    NPECL2  
    GL4  
    10  
    11  
    13  
    15  
    16  
    60  
    61  
    63  
    65  
    66  
    I/O (GLMX2)  
    "144-Pin TQFP" section is new.  
    page 2-3  
    page 2-5  
    The following pins have been changed in the "208-Pin PQFP" table:  
    Pin Number  
    Function  
    I/O (GLMX1)  
    GL1  
    NPECL1  
    PPECL1 (I/P)  
    GL2  
    Pin Number  
    128  
    129  
    132  
    134  
    Function  
    GL3  
    PPECL2 (I/P)  
    NPECL2  
    GL4  
    23  
    24  
    26  
    28  
    30  
    135  
    I/O (GLMX2)  
    The following pins have been changed in the "456-Pin PBGA" table:  
    page 2-22  
    page 2-37  
    page 2-40  
    page 2-45  
    page 2-51  
    Pin Number  
    Function  
    GL1  
    GL2  
    GL4  
    I/O (GLMX1)  
    PPECL1 (I/P)  
    Pin Number  
    Function  
    NPECL2  
    GL3  
    I/O (GLMX2)  
    NPECL1  
    PPECL2 (I/P)  
    M1  
    M2  
    M22  
    N2  
    N22  
    N23  
    N25  
    P5  
    N4  
    P26  
    The following pins have been changed in the "144-Pin FBGA" table:  
    Pin Number  
    Function  
    GL2  
    I/O (GLMX2  
    NPECL2  
    GL1  
    Pin Number  
    F9  
    )F11  
    F12  
    G1  
    G4  
    Function  
    GL4  
    PPECL2 (I/P  
    GL3  
    PPECL1 (I/P)  
    NPECL1  
    C2  
    D12  
    E11  
    F1  
    F3  
    I/O (GLMX1)  
    The following pins have been changed in the "256-Pin FBGA" table:  
    Pin Number  
    H1  
    H2  
    Function  
    GL1  
    NPECL1  
    Pin Number  
    H16  
    J1  
    Function  
    GL4  
    GL2  
    H3  
    H13  
    H14  
    I/O (GLMX1)  
    I/O (GLMX2)  
    NPECL2  
    J2  
    J13  
    J16  
    PPECL1 (I/P)  
    PPECL2 (I/P)  
    GL3  
    The following pins have been changed in the "484-Pin FBGA" table:  
    Pin Number  
    L4  
    Function  
    GL1  
    Pin Number  
    L19  
    Function  
    GL4  
    L5  
    NPECL1  
    M4  
    GL2  
    L6  
    L16  
    L17  
    I/O (GLMX1)  
    I/O (GLMX2)  
    NPECL2  
    M5  
    M16  
    M19  
    PPECL1 (I/P)  
    PPECL2 (I/P)  
    GL3  
    The following pins have been changed in the "676-Pin FBGA" table:  
    Pin Number  
    N1  
    N3  
    N5  
    N22  
    N24  
    Function  
    GL1  
    I/O (GLMX1)  
    NPECL1  
    GL3  
    Pin Number  
    N25  
    P1  
    P5  
    P22  
    P24  
    Function  
    GL4  
    GL2  
    PPECL1 (I/P)  
    I/O (GLMX2)  
    PPECL2 (I/P)  
    NPECL2  
    3-4  
    v5.2  
    PLUS  
    ProASIC  
    Flash Family FPGAs  
    Previous version  
    Changes in current version (v5.2)  
    Page  
    The following pins have been changed in the "896-Pin FBGA" table:  
    page 2-59  
    Pin Number  
    R2  
    R4  
    R5  
    R27  
    R29  
    Function  
    I/O (GLMX1)  
    NPECL1  
    GL1  
    NPECL2  
    Pin Number  
    T3  
    T4  
    T26  
    T27  
    T28  
    Function  
    GL2  
    PPECL1 (I/P)  
    PPECL2 (I/P)  
    GL4  
    I/O (GLMX2)  
    GL3  
    The following pins have been changed in the "1152-Pin FBGA" table:  
    page 2-69  
    Pin Number  
    Function  
    I/O (GLMX1)  
    NPECL1  
    GL1  
    GL2  
    PPECL1 (I/P)  
    Pin Number  
    U29  
    U31  
    V28  
    V29  
    Function  
    NPECL2  
    I/O (GLMX2)  
    PPECL2 (I/P)  
    GL4  
    U4  
    U6  
    U7  
    V5  
    V6  
    V30  
    GL3  
    Advanced v0.7  
    The "ProASICPLUS Architecture" section was updated.  
    The "Array Coordinates" section and Table 1-2 are new.  
    The "Power-Up Sequencing" section is new.  
    "I/O Features" section was updated.  
    page 1-2  
    page 1-8  
    page 1-10  
    page 1-9  
    The "Timing Control and Characteristics" section was updated. "Physical Implementation" page 1-13 to page  
    section, "Functional Description" section, "Lock Signal" section, and "PLL Configuration 1-16  
    Options" section are new.  
    "PLL Block – Top-Level View and Detailed PLL Block Diagram" section was updated.  
    Figure 1-15 was updated.  
    page 1-14  
    page 1-15  
    "Sample Implementations" section, "Adjustable Clock Delay" section, and the "Clock Skew page 1-16  
    Minimization" section are new.  
    Figure 1-16, Figure 1-17, Figure 1-18, Figure 1-19, and Figure 1-20 are new.  
    page 1-17 to page  
    1-19  
    The "PLL Electrical Specifications" section is new.  
    page 1-21  
    page 1-27  
    page 1-42  
    page 1-30  
    page 1-36  
    page 1-38  
    page 1-40  
    page 1-42  
    page 1-44  
    page 1-46  
    page 1-48  
    page 1-50  
    page 1-50  
    page 1-51  
    page 1-73  
    page 1-74  
    page 2-69  
    page i-i  
    The "Design Environment" section was updated.  
    Figure 1-26 was updated.  
    The "Calculating Typical Power Dissipation" section was updated.  
    The "DC Electrical Specifications (VDDP = 2.5 V 0.2V)" section was updated.  
    The Table 1-22 was updated.  
    The "DC Specifications (3.3 V PCI Operation)1" section was updated.  
    The "Tristate Buffer Delays" section (the figure and table) have been updated.  
    The "Output Buffer Delays" section (the figure and table) have been updated.  
    The "Input Buffer Delays" section was updated.  
    The "Global Input Buffer Delays" section was updated.  
    The "Predicted Global Routing Delay" section was updated.  
    The "Global Routing Skew" section was updated.  
    The "Sample Macrocell Library Listing" section was updated.  
    The "Pin Description" section was updated. GLMX is new.  
    The "Recommended Design Practice for VPN/VPP" section was updated.  
    Pin AK31 of FG1152 for the APA1000 changed to V .  
    PP  
    (Advanced v0.6)  
    The "Features and Benefits" on page i-i were updated.  
    The "ProASICPLUS Product Profile" on page i-i was updated.  
    The "Ordering Information" on page i-ii was updated.  
    The "Plastic Device Resources" on page i-ii was updated.  
    The "ProASICPLUS Architecture" on page 1-2 was updated.  
    page i-i  
    page i-ii  
    page i-ii  
    page 1-2  
    v5.2  
    3-5  
    PLUS  
    ProASIC  
    Flash Family FPGAs  
    Previous version  
    Changes in current version (v5.2)  
    Page  
    page 1-7  
    Advanced v0.6  
    (continued)  
    Table 1-1 was updated.  
    Figure 1-14 was updated.  
    page 1-14  
    page 1-27  
    page 1-29  
    page 1-30  
    page 1-33  
    page 1-33  
    page 1-34  
    page 1-35  
    page 1-36  
    The "Design Environment" section was updated.  
    The "Package Thermal Characteristics" section was updated.  
    The "Calculating Typical Power Dissipation" section was updated.  
    The "Absolute Maximum Ratings*" section was updated.  
    The "Programming, Storage, and Operating Limits" section was updated.  
    The ’Nominal Supply Voltages’ section was updated.  
    The "Recommended Operating Conditions" section was updated.  
    The "DC Electrical Specifications (VDDP = 2.5 V 0.2V)" section was updated.  
    The "DC Electrical Specifications (VDDP = 3.3 V 0.3 V and VDD = 2.5 V 0.2 V)" section was page 1-38  
    updated.  
    The "Synchronous Write and Read to the Same Location" section was updated.  
    page 1-61  
    The "Asynchronous Write and Synchronous Read to the Same Location" section was updated. page 1-62  
    The "Asynchronous FIFO Read" section was updated.  
    The "Pin Description" section has been updated.  
    The "Recommended Design Practice for VPN/VPP" section is new.  
    The "100-Pin TQFP" section is new.  
    page 1-67  
    page 1-73  
    page 1-74  
    page 2-1  
    page 2-45  
    page 1-74  
    page i-ii  
    The "484-Pin FBGA" section is new.  
    Advanced v0.5  
    Advanced v0.4  
    The description for the V pin has changed.  
    PN  
    The "Plastic Device Resources" section has been updated.  
    Figure 1-12 and Figure 1-13 have been updated.  
    page 1-14  
    page 1-42  
    page 1-44  
    page 1-46  
    page 1-48  
    page 2-22  
    page 2-51  
    page i-i  
    The "Tristate Buffer Delays" section has been updated.  
    The "Output Buffer Delays" section has been updated.  
    The "Input Buffer Delays" section has been updated.  
    The "Global Input Buffer Delays" section has been updated.  
    The "456-Pin PBGA" section has been updated.  
    The "676-Pin FBGA" section has been updated.  
    Advanced v0.3  
    The "ProASICPLUS Product Profile" section has been changed.  
    The "Plastic Device Resources" section has been updated.  
    The "ProASICPLUS I/O Power Supply Voltages" sectionhas been updated.  
    page i-ii  
    page 1-9  
    WDATA has ben changed to DI, and RDATA has been changed to DO to make them consistent  
    with the signal names found in the Macro Library Guide.  
    Figure 1-21 and Figure 1-22 have been updated.  
    page 1-24  
    and page 1-25  
    The "Design Environment" section and Figure 1-26 have been updated.  
    page 1-27  
    and page 1-42  
    The table in the "Package Thermal Characteristics" section has been updated.  
    The "Calculating Typical Power Dissipation" section is new.  
    page 1-29  
    page 1-30  
    page 1-33  
    page 1-34  
    page 1-36  
    The "Programming, Storage, and Operating Limits" section is new.  
    The ’Nominal Supply Voltages’ section has been updated.  
    The "DC Electrical Specifications (VDDP = 2.5 V 0.2V)" section was updated.  
    The "DC Electrical Specifications (VDDP = 3.3 V 0.3 V and VDD = 2.5 V 0.2 V)" section was page 1-38  
    updated.  
    The "Recommended Operating Conditions" section was updated.  
    The "ProASICPLUS Clock Management System" section was updated.  
    page 1-35  
    page 1-13  
    3-6  
    v5.2  
    PLUS  
    ProASIC  
    Flash Family FPGAs  
    Previous version  
    Changes in current version (v5.2)  
    Page  
    Advanced v0.3  
    (continued)  
    Figure 1-14 was updated.  
    page 1-14  
    Figure 1-13 is new.  
    page 1-12  
    Tables 5, 6, and 7 from Advanced v0.3 were removed.  
    The "Memory Block SRAM Interface Signals" section was updated.  
    The "Memory Block FIFO Interface Signals" section was updated.  
    All pinout tables have been updated, and several packages are new:  
    page 1-24  
    page 1-25  
    208-Pin PQFP – APA150, APA300, APA450, APA600  
    456-Pin PBGA – APA150, APA300, APA450, APA600  
    144-Pin FBGA – APA150, APA300, APA450  
    256-Pin FBGA – APA150, APA300, APA450, APA600  
    676-Pin FBGA – APA600  
    Advanced v0.1  
    Figure 1-23 has been updated.  
    page 1-26  
    Data Sheet Categories  
    In order to provide the latest information to designers, some datasheets are published before data has been fully  
    characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet  
    Supplement." The definition of these categories are as follows:  
    Product Brief  
    The product brief is a summarized version of a datasheet (advanced or production) containing general product  
    information. This brief gives an overview of specific device and family information.  
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    This datasheet version contains initial estimated information based on simulation, other products, devices, or speed  
    grades. This information can be used as estimates, but not for production.  
    Unmarked (production)  
    This datasheet version contains information that is considered to be final.  
    Datasheet Supplement  
    The datasheet supplement gives specific device information for a derivative family that differs from the general family  
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    for specifications that do not differ between the two families.  
    Export Administration Regulations (EAR)  
    The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could  
    require an approved export license prior to export from the United States. An export includes release of product or  
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    v5.2  
    3-7  
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    http://www.actel.com  
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