1
I/Os Per Package
ProASIC3E Devices
Cortex-M1 Devices2
A3PE600
A3PE1500 3
M1A3PE1500
I/O Types
A3PE3000 3
M1A3PE3000
Package
PQ208
FG256
FG324
FG484
FG676
FG896
Notes:
147
165
–
65
79
–
147
65
–
147
65
–
–
–
–
–
221
341
–
110
168
–
270
–
135
–
280
444
–
139
222
–
–
–
620
310
1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3E Flash Family FPGAs
handbook to ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per
minibank (group of I/Os).
6. "G" indicates RoHS-compliant packages. Refer to the "ProASIC3E Ordering Information" on page III for the location of
the "G" in the part number.
II
v1.0
ACTEL [ Actel Corporation ]
