ProASIC3E DC and Switching Characteristics
Previous Version
Changes in Current Version (v1.2)
Page
Advance v0.6
(continued)
Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E
Devices was updated.
2-64
Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
2-40
The "VCCPLF PLL Supply Voltage" section was updated.
2-50
2-50
2-51
The "VPUMP Programming Supply Voltage" section was updated.
The "GL Globals" section was updated to include information about direct
input into quadrant clocks.
VJTAG was deleted from the "TCK Test Clock" section.
2-51
2-51
In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
Ambient was deleted from Table 3-2 • Recommended Operating Conditions.
VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
3-2
3-2
Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured
on quiet I/Os).
In EQ 3-2, 150 was changed to 110 and the result changed to 5.88.
3-5
3-5
Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated.
Table 3-5 • Package Thermal Resistivities was updated.
3-5
3-8
Table 3-10 • Different Components Contributing to the Dynamic Power
Consumption in ProASIC3E Devices was updated.
tWRO and tCCKH were added to Table 3-94 • RAM4K9 and Table 3-74 to
3-95 • RAM512X18.
3-74
The note in Table 3-24 • I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
3-23
Figure 3-43 • Write Access After Write onto Same Address, Figure 3-71 to
3-44 • Read Access After Write onto Same Address, and Figure 3-45 • Write
Access After Read onto Same Address are new.
3-73
Figure 3-53 • Timing Diagram was updated.
3-80
N/A
Advance v0.4
(October 2005)
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
The term flow-through was changed to pass-through.
Figure 2-8 • Very-Long-Line Resources was updated.
The footnotes in Figure 2-27 • CCC/PLL Macro were updated.
N/A
2-8
2-28
2-24
The Delay Increments in the Programmable Delay Blocks specification in
Figure 2-24 • ProASIC3E CCC Options.
The "SRAM and FIFO" section was updated.
The "RESET" section was updated.
2-21
2-25
2-25
2-25
2-27
2-28
The "WCLK and RCLK" section was updated.
The "RESET" section was updated.
The "RESET" section was updated.
The "Introduction" of the "Introduction" section was updated.
2-84
v1.2