Device Architecture
CLK1
ADD1
DI1
tAS tAH
A0
A2
D2
A3
D3
tDS tDH
D0
tWRO
CLK2
tAS tAH
A1
A0
A4
ADD2
DO2
tCKQ1
Dn
D0
D1
(flow-through)
tCKQ2
DO2
(Pipelined)
Dn
D0
Figure 2-53 • One Port Write / Other Port Read Same
CLK1
tAS
tAH
A0
A3
D3
ADD1
DI1
A1
D2
tDS
tDH
D1
tCCKH
CLK2
WEN_B1
WEN_B2
tAS
tAH
A0
A4
A0
D0
ADD2
DI2
D4
tCKQ1
DO2
(pass-through)
D0
Dn
tCKQ2
DO2
(pipelined)
D0
Dn
Figure 2-54 • Write Access After Write onto Same Address
2-68
Preliminary v1.7