Device Architecture
Flash Memory Block Diagram
A simplified diagram of the flash memory block is shown in Figure 2-32.
Output
MUX
ECC
Logic
Flash Array = 64 Sectors
RD[31:0]
Page Buffer = 8 Blocks
Plus AUX Block
Block Buffer
(128 bits)
WD[31 :0]
ADDDR[17:0]
DATAWIDTH[1:0]
REN
READNEXT
PAGESTATUS
WEN
ERASEPAGE
PROGRAM
SPAREPAGE
AUXBLOCK
UNPROTECTPAGE
OVERWRITEPAGE
DISCARDPAGE
OVERWRITEPROTECT
PAGELOSSPROTECT
PIPE
Control
Logic
LOCKREQUEST
CLK
RESET
STATUS[1:0]
BUSY
Figure 2-32 • Flash Memory Block Diagram
The logic consists of the following sub-blocks:
•
Flash Array
Contains all stored data. The flash array contains 64 sectors, and each sector contains 33
pages of data.
•
•
•
Page Buffer
A page-wide volatile register. A page contains 8 blocks of data and an AUX block.
Block Buffer
Contains the contents of the last block accessed. A block contains 128 data bits.
ECC Logic
The FB stores error correction information with each block to perform single-bit error
correction and double-bit error detection on all data blocks.
2-44
Preliminary v1.7
ACTEL [ Actel Corporation ]
