Device Architecture
The system application, Level 3, is the larger user application that utilizes one or more applets.
Designing at the highest level of abstraction supported by the Actel Fusion technology stack, the
application can be easily created in FPGA gates by importing and configuring multiple applets.
In fact, in some cases an entire FPGA system design can be created without any HDL coding.
An optional MCU enables a combination of software and HDL-based design methodologies. The
MCU can be on-chip or off-chip as system requirements dictate. System portioning is very flexible,
allowing the MCU to reside above the applets or to absorb applets, or applets and backbone, if
desired.
The Actel Fusion technology stack enables a very flexible design environment. Users can engage in
design across a continuum of abstraction from very low to very high.
Core Architecture
VersaTile
Based upon successful Actel ProASIC3/E logic architecture, Fusion devices provide granularity
comparable to gate arrays. The Fusion device core consists of a sea-of-VersaTiles architecture.
As illustrated in Figure 2-2, there are four inputs in a logic VersaTile cell, and each VersaTile can be
configured using the appropriate flash switch connections:
•
•
•
•
Any 3-input logic function
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set (on a 4th input)
VersaTiles can flexibly map the logic and sequential gates of a design. The inputs of the VersaTile
can be inverted (allowing bubble pushing), and the output of the tile can connect to high-speed,
very-long-line routing resources. VersaTiles and larger functions are connected with any of the four
levels of routing hierarchy.
When the VersaTile is used as an enable D-flip-flop, the SET/CLR signal is supported by a fourth
input, which can only be routed to the core cell over the VersaNet (global) network.
2-2
Preliminary v1.7
ACTEL [ Actel Corporation ]
