Actel Fusion Mixed-Signal FPGAs
Modes of Operation
There are two read modes and one write mode:
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Read Nonpipelined (synchronous—1 clock edge): In the standard read mode, new data is
driven onto the RD bus in the same clock cycle following RA and REN valid. The read address
is registered on the read port clock active edge, and data appears at RD after the RAM
access time. Setting PIPE to OFF enables this mode.
Read Pipelined (synchronous—2 clock edges): The pipelined mode incurs an additional clock
delay from the address to the data but enables operation at a much higher frequency. The
read address is registered on the read port active clock edge, and the read data is registered
and appears at RD after the second read clock edge. Setting PIPE to ON enables this mode.
Write (synchronous—1 clock edge): On the write clock active edge, the write data is written
into the SRAM at the write address when WEN is HIGH. The setup times of the write address,
write enables, and write data are minimal with respect to the write clock. Write and read
transfers are described with timing requirements in the "SRAM Characteristics" section on
page 2-66 and the "FIFO Characteristics" section on page 2-77.
RAM Initialization
Each SRAM block can be individually initialized on power-up by means of the JTAG port using the
UJTAG mechanism (refer to the "JTAG IEEE 1532" section on page 2-224 and the Fusion SRAM/FIFO
Blocks application note). The shift register for a target block can be selected and loaded with the
proper bit configuration to enable serial loading. The 4,608 bits of data can be loaded in a single
operation.
Preliminary v1.7
2-65
ACTEL [ Actel Corporation ]
