Actel Fusion Mixed-Signal FPGAs
Table 2-25 • Flash Memory Block Timing (continued)
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
2.52
0.00
2.19
0.00
2.27
0.00
3.33
0.00
2.52
0.00
1.16
0.00
1.25
0.00
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUDISCARDPG
tHDDISCARDPG
tSUOVERWRPRO
tHDOVERWRPRO
tSUPGLOSSPRO
tHDPGLOSSPRO
tSUPGSTAT
Discard Page Setup Time for the Control Logic
Discard Page Hold Time for the Control Logic
Overwrite Protect Setup Time for the Control Logic
Overwrite Protect Hold Time for the Control Logic
Page Loss Protect Setup Time for the Control Logic
Page Loss Protect Hold Time for the Control Logic
Page Status Setup Time for the Control Logic
Page Status Hold Time for the Control Logic
Over Write Page Setup Time for the Control Logic
Over Write Page Hold Time for the Control Logic
Lock Request Setup Time for the Control Logic
Lock Request Hold Time for the Control Logic
Reset Recovery Time
1.88
0.00
1.64
0.00
1.69
0.00
2.49
0.00
1.88
0.00
0.87
0.00
0.94
0.00
2.14
0.00
1.86
0.00
1.93
0.00
2.83
0.00
2.14
0.00
0.99
0.00
1.07
0.00
tHDPGSTAT
tSUOVERWRPG
tHDOVERWRPG
tSULOCKREQUEST
tHDLOCKREQUEST
tRECARNVM
tREMARNVM
Reset Removal Time
tMPWARNVM
Asynchronous Reset Minimum Pulse Width for the 10.00 12.50 12.50
Control Logic
tMPWCLKNVM
tFMAXCLKNVM
Clock Minimum Pulse Width for the Control Logic
Maximum Frequency for Clock for the Control Logic
4.00
5.00
5.00
ns
100.00 80.00 80.00
MHz
Preliminary v1.7
2-55
ACTEL [ Actel Corporation ]
