Actel Fusion Mixed-Signal FPGAs
Table 2-7 • AFS250 Global Resource Timing
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Min.1 Max.2 Min.1 Max.2
Min.1
Max.2 Units
Input LOW Delay for Global Clock
Input HIGH Delay for Global Clock
0.89
0.88
1.12
1.14
1.02
1.00
1.27
1.30
1.20
1.50
1.53
ns
ns
ns
tRCKH
1.17
tRCKMPWH Minimum Pulse Width HIGH for Global
Clock
tRCKMPWL
Minimum Pulse Width LOW for Global
Clock
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.26
0.30
0.35
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
Table 2-8 • AFS090 Global Resource Timing
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
Input LOW Delay for Global Clock
Input HIGH Delay for Global Clock
0.84
0.83
1.07
1.10
0.96
0.95
1.21
1.25
1.13
1.12
1.43
1.47
ns
ns
ns
tRCKH
tRCKMPWH
Minimum Pulse Width HIGH for Global
Clock
tRCKMPWL
Minimum Pulse Width LOW for Global
Clock
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.27
0.30
0.36
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
Preliminary v1.7
2-19
ACTEL [ Actel Corporation ]
