Actel Fusion Mixed-Signal FPGAs
The output of the VersaTile is F2 when the connection is to the ultra-fast local lines, or YL when the
connection is to the efficient long-line or very-long-line resources (Figure 2-2).
0
1
Y
Pin 1
Data
X3
0
1
0
1
F2
YL
0
1
CLK
X2
CLR/
Enable
X1
CLR
XC*
Ground
Legend:
Via (hard connection)
Switch (flash connection)
Note: *This input can only be connected to the global clock distribution network.
Figure 2-2 • Fusion Core VersaTile
Preliminary v1.7
2-3