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A54SX16A-PQ208A 参数 Datasheet PDF下载

A54SX16A-PQ208A图片预览
型号: A54SX16A-PQ208A
PDF下载: 下载PDF文件 查看货源
内容描述: SX -A汽车系列FPGA [SX-A Automotive Family FPGAs]
分类和应用:
文件页数/大小: 68 页 / 498 K
品牌: ACTEL [ Actel Corporation ]
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General Description  
Actel's SX-A family of FPGAs features a sea-of-modules  
architecture. SX-A devices simplify design time, enable  
dramatic reductions in design costs and power  
consumption, and further decrease time-to-market for  
SX-A Family Architecture  
Programmable Interconnect Element  
performance-intensive  
applications.  
With  
the  
The SX-A family provides efficient use of silicon by  
locating the routing interconnect resources between the  
top two metal layers (Figure 1-1). This completely  
eliminates the channels of routing and interconnect  
resources between logic modules (as implemented on  
SRAM FPGAs and previous generations of antifuse  
FPGAs), and enables the entire floor of the device to be  
spanned with an uninterrupted grid of logic modules.  
automotive temperature grade support (-40°C to 125°C),  
the SX-A devices can address many in-cabin telematics  
and automobile interconnect applications.  
Actel’s SX-A architecture features two types of logic  
modules, the combinatorial cell (C-cell) and the register  
cell (R-cell), each optimized for fast and efficient  
mapping of synthesized logic functions. The routing and  
interconnect resources are in the metal layers above the  
logic modules, providing optimal use of silicon. This  
enables the entire floor of the device to be spanned with  
an uninterrupted grid of fine-grained, synthesis-friendly  
logic modules (or “sea-of-modules”), which reduces the  
distance signals have to travel between logic modules. To  
minimize signal propagation delay, SX-A devices employ  
both local and general routing resources. The high-speed  
local routing resources (DirectConnect and FastConnect)  
enable very fast local signal propagation that is optimal  
for fast counters, state machines, and datapath logic.  
The general system of segmented routing tracks allows  
any logic module in the array to be connected to any  
other logic or I/O module. Within this system,  
propagation delay is minimized by limiting the number  
of antifuse interconnect elements to five (90 percent of  
connections typically use only three or fewer antifuses).  
The unique local and general routing structure featured  
in SX-A devices gives fast and predictable performance,  
allows 100% pin-locking with full logic utilization,  
enables concurrent PCB development, reduces design  
time, and allows designers to achieve performance goals  
with minimum effort.  
Interconnection between these logic modules is achieved  
using Actel’s patented metal-to-metal programmable  
antifuse interconnect elements. The antifuses are  
normally open circuit and, when programmed, form a  
permanent low-impedance connection.  
The extremely small size of these interconnect elements  
gives the automotive-grade SX-A devices abundant  
routing resources and provides excellent protection  
against design pirating. Reverse engineering is virtually  
impossible because it is extremely difficult to distinguish  
between programmed and unprogrammed antifuses,  
and since SX-A is a nonvolatile, single-chip solution,  
there is no configuration bitstream to intercept.  
Additionally, the interconnect (i.e., the antifuses and  
metal tracks) have lower capacitance and lower  
resistance than any other device of similar capacity,  
leading to the fastest signal propagation in the industry.  
Logic Module Design  
The SX-A family architecture is described as a “sea-of-  
modules” architecture because the entire floor of the  
device is covered with a grid of logic modules with  
virtually no chip area lost to interconnect elements or  
routing. Actel’s SX-A family provides two types of logic  
modules, the register cell (R-cell) and the combinatorial  
cell (C-cell).  
Further complementing SX-A’s flexible routing structure  
is a hardwired, constantly loaded clock network that has  
been tuned to provide fast clock propagation with  
minimal clock skew. Additionally, the high performance  
of the internal logic has eliminated the need to embed  
latches or flip-flops in the I/O cells to achieve fast clock-  
to-out or fast input set-up times. SX-A devices have easy-  
to-use I/O cells that do not require HDL instantiation,  
facilitating design re-use and reducing design and  
verification time.  
The R-cell contains a flip-flop featuring asynchronous  
clear, asynchronous preset, and clock enable (using the  
S0 and S1 lines) control signals (Figure 1-2 on page 1-3).  
The R-cell registers feature programmable clock polarity  
selectable on a register-by-register basis. This provides  
additional flexibility while allowing mapping of  
synthesized functions into the SX-A FPGA. The clock  
source for the R-cell can be chosen from either the  
hardwired clock, the routed clocks, or internal logic.  
v2.2  
1-1  
Routing Tracks  
Amorphous Silicon/  
Dielectric Antifuse  
Tungsten Plug Via  
Metal 4  
Metal 3  
Tungsten Plug Via  
Metal 2  
Metal 1  
Tungsten Plug Contact  
Silicon Substrate  
Note: A54SX72A has four layers of metal with the antifuse between Metal 3 and Metal 4. A54SX08A, A54SX16A, and A54SX32A have  
three layers of metal with antifuse between Metal 2 and Metal 3.  
Figure 1-1 SX-A Family Interconnect Elements  
The C-cell implements a range of combinatorial functions  
Chip Architecture  
of up to five inputs (Figure 1-3 on page 1-3). Inclusion of  
The SX-A family’s chip architecture provides a unique  
the DB input and its associated inverter function allows  
approach to module organization and chip routing that  
more than 4,000 combinatorial functions to be  
delivers the best register/logic mix for a wide variety of  
implemented in a single module in the SX-A architecture.  
new and emerging applications.  
The inverter function improves flexibility in the  
architecture; for instance a 3-input exclusive-OR function  
can be integrated into a single C-cell. At the same time,  
Module Organization  
the C-cell structure is extremely synthesis friendly,  
The C-cell and R-cell logic modules are arranged into  
simplifying the overall design and reducing synthesis  
horizontal groups called Clusters. There are two types of  
time.  
Clusters: Type 1 contains two C-cells and one R-cell, while  
Two C cells can be combined together to create a flip-  
Type 2 contains one C-cell and two R-cells.  
flop to imitate an R-cell via the user of the CC macro. This  
Clusters are further organized into SuperClusters for  
is particularly useful when implementing paths which are  
even better design efficiency and device performance  
not timing-critical or if the designer needs more R-cells.  
(Figure 1-4 on page 1-4). SuperCluster 1 is a two-wide  
More information about CC macro can be found in  
grouping of Type 1 Clusters. SuperCluster 2 is a two-wide  
group containing one Type 1 Cluster and one Type 2  
Cluster. SX-A devices feature more SuperCluster 1  
modules than SuperCluster 2 modules because designers  
typically require significantly more combinatorial logic  
than flip-flops.  
Actel's Maximizing Logic Utilization in eX, SX and SX-A  
FPGA Devices Using CC Macros Application Note.  
1-2  
v2.2  
Routed  
Data Input  
S1  
S0  
PRE  
DirectConnect  
Input  
D
Q
Y
HCLK  
CLKA,  
CLKB,  
CLR  
Internal Logic  
CKS  
CKP  
Figure 1-2 R-Cell  
D0  
D1  
Y
D2  
D3  
Sa  
Sb  
B1  
DB  
A1  
A0 B0  
Figure 1-3 C-Cell  
DirectConnect is a horizontal routing resource that  
provides connections from a C-cell to its neighboring R-  
cell in a given SuperCluster. DirectConnect uses a  
hardwired signal path requiring no programmable  
interconnection to achieve its fast signal propagation  
time of less than 0.1 ns.  
Routing Resources  
Clusters and SuperClusters can be connected through the  
use of two innovative local routing resources called  
FastConnect and DirectConnect, which enable extremely  
fast and predictable interconnection of modules within  
Clusters and SuperClusters (Figure 1-5 on page 1-4 and  
Figure 1-6 on page 1-5). This routing architecture also  
dramatically reduces the number of antifuses required to  
FastConnect enables horizontal routing between any  
two logic modules within a given SuperCluster and  
vertical routing with the SuperCluster immediately  
below it. Only one programmable connection is used in a  
FastConnect path, delivering a maximum pin-to-pin  
propagation time of 0.5 ns.  
complete  
a circuit, ensuring the highest possible  
performance.  
v2.2  
1-3  
R-Cell  
C-Cell  
D0  
D1  
Routed  
Data Input  
S1  
S0  
PRE  
CLR  
Y
D2  
D3  
DirectConnect  
Input  
D
Q
Y
Sb  
Sa  
HCLK  
CLKA,  
CLKB,  
DB  
Internal Logic  
CKS  
CKP  
A0 B0  
A1 B1  
Cluster 1  
Cluster 1  
Cluster 2  
Cluster 1  
Type 1 SuperCluster  
Type 2 SuperCluster  
Figure 1-4 Cluster Organization  
DirectConnect  
• No antifuses  
• 0.1 ns maximum routing delay  
FastConnect  
• One antifuse  
• 0.3 ns maximum routing delay  
Routing Segments  
• Typically 2 antifuses  
• Max. 5 antifuses  
Type 1 SuperClusters  
Figure 1-5 DirectConnect and FastConnect for Type 1 SuperClusters  
1-4  
v2.2  
DirectConnect  
• No antifuses  
• 0.1 ns maximum routing delay  
FastConnect  
• One antifuse  
• 0.3 ns maximum routing delay  
Routing Segments  
• Typically 2 antifuses  
• Max. 5 antifuses  
Type 2 SuperClusters  
Figure 1-6 DirectConnect and FastConnect for Type 2 SuperClusters  
In addition to DirectConnect and FastConnect, the  
architecture makes use of two globally oriented routing  
resources known as segmented routing and high-drive  
routing. Actel’s segmented routing structure provides a  
variety of track lengths for extremely fast routing  
between SuperClusters. The exact combination of track  
lengths and antifuses within each path is chosen by the  
fully automatic place-and-route software to minimize  
signal propagation delays.  
Two additional clocks (CLKA, CLKB) are global clocks that  
can be sourced from external pins or from internal logic  
signals within the automotive-grade SX-A device. CLKA  
and CLKB may be connected to sequential cells or to  
combinational logic. If CLKA or CLKB pins are not used or  
sourced from signals, then these pins must be set as LOW  
or HIGH on the board. They must not be left floating  
(except in the A54SX72A where these clocks can be  
configured as regular I/Os and can float). Figure 1-8 on  
page 1-6 describes the CLKA and CLKB circuit used in SX-  
A devices with the exception of A54SX72A.  
Clock Resources  
In addition to CLKA and CLKB, the A54SX72A device  
provides four quadrant clocks (QCLKA, QCLKB, QCLKC,  
QCLKD – corresponding to bottom-left, bottom-right,  
top-left, and top-right locations on the die, respectively),  
which can be sourced from external pins or from internal  
logic signals within the device. Each of these clocks can  
individually drive up to a quarter of the chip, or they can  
be grouped together to drive multiple quadrants. If  
QCLKs are not used as quadrant clocks, they will behave  
as regular I/Os. Bidirectional clock buffers are also  
available on the A54SX72A. The CLKA, CLKB, and QCLK  
circuits for A54SX72A are shown in Figure 1-9 on page 1-  
6. Note that bidirectional clock buffers are only available  
in A54SX72A. For more information, refer to the “Pin  
Description” on page 1-38.  
Actel’s high-drive routing structure provides three clock  
networks (Table 1-1). The first clock, called HCLK, is  
hardwired from the HCLK buffer to the clock select MUX  
in each R-cell. HCLK cannot be connected to  
combinatorial logic. This provides a fast propagation  
path for the clock signal, enabling the 5.6 ns clock-to-out  
(pad-to-pad) performance of the auotmotive-grade SX-A  
devices. The hardwired clock is tuned to provide clock  
skew less than 0.3 ns worst case. If not used, this pin must  
be set as LOW or HIGH on the board. It must not be left  
floating. Figure 1-7 on page 1-6 describes the clock  
circuit used for the constant load HCLK. When the device  
is powered up and TRST is not grounded, HCLK does not  
function until the fourth clock cycle. This prevents  
possible false outputs due to a slow power-on-reset  
signal and fast start-up clock circuit. To activate HCLK  
from the first cycle, TRST pin must be reserved in the  
Designer software and the pin must be tied to GND on  
the board.  
For more information on how to use quadrant clocks in  
the A54SX72A device, refer to the Global Clock Networks  
in Actel’s Antifuse Devices and Using A54SX72A and  
RT54SX72S Quadrant Clocks application notes.  
v2.2  
1-5  
Table 1-1 SX-A Clock Resources  
A54SX08A  
A54SX16A  
A54SX32A  
A54SX72A  
Routed Clocks (CLKA, CLKB)  
2
1
0
2
1
0
2
1
0
2
1
4
Hardwired Clocks (HCLK)  
Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD)  
Constant Load  
Clock Network  
HCLKBUF  
Figure 1-7 SX-A HCLK Clock Pad  
Clock Network  
From Internal Logic  
CLKBUF  
CLKBUFI  
CLKINT  
CLKINTI  
Figure 1-8 SX-A Routed Clock Structure Except for A54SX72A  
OE  
From Internal Logic  
To Internal Logic  
Clock Network  
From Internal Logic  
CLKBUF  
CLKBUFI  
CLKINT  
QCLKBUF  
QCLKBUFI  
QCLKINT  
CLKINTI  
CLKBIBUF  
CLKBIBUFI  
QCLKINTI  
QCLKBIBUF  
QCLKBIBUFI  
Figure 1-9 A54SX72A Routed Clock and QClock Structure  
1-6  
v2.2  
I/O Modules  
Other Architectural Features  
Each user I/O on an automotive-grade SX-A device can be  
configured as an input, an output, a tristate output, or a  
bidirectional pin. I/O pins can be set for 2.5 V or 3.3 V  
operation through VCCI. SX-A I/Os, combined with array  
registers, can achieve clock-to-output-pad timing of  
5.6 ns even without the dedicated I/O registers. In most  
FPGAs, I/O cells that have embedded latches and flip-  
flops require instantiation in HDL code; this is a design  
complication not encountered in SX-A FPGAs. Fast pin-  
to-pin timing ensures that the device is able to interface  
with any other device in the system, which in turn  
enables parallel design of system components and  
reduces overall design time. All unused I/Os are  
configured as tristate outputs by Actel’s Designer  
software, for maximum flexibility when designing new  
boards or migrating existing designs.  
Technology  
The automotive-grade SX-A devices are implemented on  
a high-voltage, twin-well CMOS process using 0.22 µ  
design rules. The metal-to-metal antifuse is comprised of  
a combination of amorphous silicon and dielectric  
material with barrier metals and has a programmed  
(“on” state) resistance of 25 with capacitance of 1.0 fF  
for low signal impedance.  
Performance  
The combination of architectural features described  
above enables automotive-grade SX-A devices to  
operate with internal clock frequencies of 250 MHz,  
enabling fast execution of even complex logic functions  
at extended tempetature ranges. Thus, the automotive-  
grade SX-A devices are an optimal platform upon which  
to integrate the functionality previously contained in  
multiple CPLDs. In addition, designs that previously  
would have required a gate array to meet performance  
goals can be integrated into an SX-A device with  
dramatic improvements in cost and time-to-market.  
Using timing-driven place-and-route tools, designers can  
achieve highly deterministic device performance.  
SX-A inputs should be driven by high-speed push-pull  
devices with a low-resistance pull-up device. If the input  
voltage is greater than VCCI and a fast push-pull device is  
NOT used, the high-resistance pull-up of the driver and  
the internal circuitry of the SX-A I/O may create a voltage  
divider. This voltage divider could pull the input voltage  
below specification for some devices connected to the  
driver. A logic '1' may not be correctly presented in this  
case. For example, if an open drain driver is used with a  
pull-up resistor to 3.3V to provide the logic '1' input, and  
VCCI is set to 2.5 V on the SX-A device, the input signal  
may be pulled down by the SX-A input.  
User Security  
Each I/O module has an available power-up resistor of  
approximately 50 kthat can configure the I/O in a  
known state during power-up. Just slightly before VCCA  
reaches 2.5 V, the resistors are disabled, so the I/Os will  
be controlled by user logic. See Table 1-2 on page 1-8  
and Table 1-3 on page 1-8 for more information  
concerning available I/O features.  
The Actel FuseLock advantage ensures that unauthorized  
users will not be able to read back the contents of an  
Actel antifuse FPGA. In addition to the inherent  
strengths of the architecture, special security fuses that  
prevent internal probing and overwriting are hidden  
throughout the fabric of the device. They are located  
such that they cannot be accessed or bypassed without  
destroying the rest of the device, making both invasive  
and more-subtle noninvasive attacks ineffective against  
Actel antifuse FPGAs.  
Hot Swapping  
During power-up/down (or partial up/down), all I/Os are  
tristated. VCCA and VCCI do not have to be stable during  
power-up/down. After the SX-A device is plugged into an  
electrically active system, the device will not degrade the  
reliability of or cause damage to the host system. The  
device’s output pins are driven to a high impedance state  
until normal chip operating conditions are reached.  
Table 1-4 on page 1-8 summarizes the VCCA voltage at  
which the I/Os behave according to the user’s design for  
an SX-A device at room temperature for various ramp-up  
rates. The data reported assumes a linear ramp-up  
profile to 2.5V. For more information on power-up and  
hot-swapping, refer to the application note, Actel SX-A  
and RT54SX-S Devices in Hot-Swap and Cold-Sparing  
Applications.  
Look for this symbol to ensure your valuable IP is secure.  
u
e
For more information, refer to Actel’s Implementation of  
Security in Actel Antifuse FPGAs application note.  
v2.2  
1-7  
Table 1-2 I/O Features  
Function  
Description  
Input Buffer Threshold Selections  
3.3V PCI, LVTTL  
2.5V LVCMOS2  
Flexible Output Driver  
Output Buffer  
3.3V PCI, LVTTL  
2.5V LVCMOS2  
"Hot-Swap" Capability (except 3.3V PCI)  
I/O on an unpowered device does not sink current  
Can be used for “cold-sparing”  
Selectable on an individual I/O basis  
Individually selectable slew rate, high slew or low slew (The default is high slew rate).  
The slew is only affected on the falling edge of an output. Rising edges of outputs are  
not affected.  
Power-Up  
Individually selectable pull-ups and pull-downs during power-up (default is to power-up  
in tristate)  
Enables deterministic power-up of device  
V
CCA and VCCI can be powered in any order  
Table 1-3 I/O Characteristics for All I/O Configurations  
Hot Swappable  
Slew Rate Control  
Power-Up Resistor  
Pull-up or pull-down  
Pull-up or pull-down  
LVTTL, LVCMOS2  
3.3V PCI  
Yes  
No  
Yes. Only affects falling edges of outputs  
No. High slew rate only  
Table 1-4 Power-up Time at which I/Os Become Active  
Supply Ramp Rate 0.25V/µs 0.025V/µs  
5V/ms  
ms  
2.5V/ms  
ms  
0.5V/ms  
ms  
0.25V/ms  
0.1V/ms 0.025V/ms  
Units  
µs  
10  
10  
10  
10  
µs  
96  
ms  
5.4  
4.7  
5.2  
5.0  
ms  
12.9  
11.0  
12.1  
12.1  
ms  
50.8  
41.6  
47.2  
47.2  
A54SX08A  
A54SX16A  
A54SX32A  
A54SX72A  
0.34  
0.36  
0.46  
0.41  
0.65  
2.7  
100  
100  
100  
0.62  
2.5  
0.74  
2.8  
0.67  
2.6  
To select Dedicated mode, users need to reserve the JTAG  
pins in Actel’s Designer software. To reserve the JTAG  
pins, users can check the "Reserve JTAG" box in "Device  
Selection Wizard" (Figure 1-10 on page 1-9).  
Boundary-Scan Testing (BST)  
Automotive-grade SX-A devices are IEEE 1149.1  
compliant and offer superior diagnostic and testing  
capabilities by providing Boundary Scan Testing (BST)  
and probing capabilities. The BST function is controlled  
through the special JTAG pins (TMS, TDI, TCK, TDO, and  
TRST). The functionality of the JTAG pins is defined by  
two available modes: Dedicated and Flexible. TMS  
cannot be employed as user I/O in either mode.  
To select Dedicated mode, users need to reserve the JTAG  
pins in Actel's Designer software by checking the  
"Reserve JTAG" box in "Device Selection Wizard"  
(Figure 1-10 on page 1-9). JTAG pins comply with LVTTL/  
TTL I/O specification regardless of whether they are used  
as a user I/O or a JTAG I/O. Refer to the “3.3V LVTTL  
Electrical Specifications” on page 1-13 and “2.5V  
LVCMOS2 Electrical Specifications” on page 1-14 for  
detailed specifications.  
Dedicated Mode  
In Dedicated mode, all JTAG pins are reserved for BST;  
designers cannot use them as regular I/Os. An internal  
pull-up resistor is automatically enabled on both TMS  
and TDI pins, and the TMS pin will function as defined in  
the IEEE 1149.1 (JTAG) specification.  
1-8  
v2.2  
Upon power-up, the TAP controller enters the Test-Logic-  
Reset state. In this state, TDI, TCK and TDO function as  
user I/Os. The TDI, TCK, and TDO are transformed from  
user I/Os into BST pins when a rising edge on TCK is  
detected while TMS is at logic low. To return to Test-  
Logic Reset state, TMS must be high for at least five TCK  
cycles. An external 10Kpull-up resistor to VCCI should  
be placed on the TMS pin to pull it HIGH by default.  
Table 1-5  
describes  
the  
different  
configuration  
requirements of BST pins and their functionality in  
different modes.  
TRST Pin  
Figure 1-10 Device Selection Wizard  
The TRST pin functions as a dedicated Boundary-Scan  
Reset pin when the "Reserve JTAG Test Reset" option is  
selected as shown in Figure 1-10 on page 1-9. An internal  
pull-up resistor is permanently enabled on the TRST pin  
in this mode. Actel recommends connecting this pin to  
ground in normal operation to keep the JTAG state  
controller in the Test-Logic-Reset state. When JTAG is  
being used, it can be left floating or be driven high.  
Flexible Mode  
In Flexible mode, TDI, TCK, and TDO may be employed as  
either user I/Os or as JTAG input pins. The internal  
resistors on the TMS and TDI pins are not present in  
flexible JTAG mode.  
To select the Flexible mode, users need to uncheck the  
"Reserve JTAG" box in "Device Selection Wizard" in  
Actel’s Designer software. In Flexible mode, TDI, TCK and  
TDO pins may function as user I/Os or BST pins. The  
functionality is controlled by the BST TAP controller. The  
TAP controller receives two control inputs, TMS and TCK.  
When the "Reserve JTAG Test Reset" option is not  
selected, this pin will function as a regular I/O. If unused  
as an I/O in the design, it will be configured as a tristated  
output.  
Table 1-5 Boundary-Scan Pin Configurations and Functions  
Mode  
Designer "Reserve JTAG" Selection  
Checked  
TAP Controller State  
Any  
Dedicated (JTAG)  
Flexible (User I/O)  
Flexible (JTAG)  
Unchecked  
Unchecked  
Test-Logic-Reset  
Any EXCEPT Test-Logic-Reset  
Probing Capabilities  
Automotive-grade SX-A devices also provide an internal  
probing capability that is accessed with the JTAG pins.  
The Silicon Explorer II Diagnostic Hardware is used to  
control the TDI, TCK, TMS and TDO pins to select the  
desired nets for debugging. The user assigns the selected  
internal nets in Actel's Silicon Explorer II software to the  
PRA/PRB output pins for observation. Silicon Explorer II  
automatically places the device into JTAG mode.  
However, probing functionality is only activated when  
the TRST pin is driven high or left floating, allowing the  
internal pull-up resistor to pull TRST to HIGH. If the TRST  
pin is held LOW, the TAP controller remains in the Test-  
Logic-Reset state so no probing can be performed.  
However, the user must drive the TRST pin HIGH or allow  
the internal pull-up resistor to pull TRST HIGH.  
When selecting the "Reserve Probe Pin" box as shown in  
Figure 1-10 on page 1-9, direct the layout tool to reserve  
the PRA and PRB pins as dedicated outputs for probing.  
This "reserve" option is merely a guideline. If the  
designer assigns user I/Os to the PRA and PRB pins and  
selects the "Reserve Probe Pin" option, Designer Layout  
will override the "Reserve Probe Pin" option and place  
the user I/Os on those pins.  
To allow probing capabilities, the security fuse must not  
be programmed. Programming the security fuse disables  
the probe circuitry. Table 1-6 on page 1-10 summarizes  
the possible device configurations for probing once the  
device leaves the "Test-Logic-Reset" JTAG state.  
v2.2  
1-9  
Table 1-6 Device Configuration Options for Probe Capability (TRST pin reserved)  
Security Fuse  
Programmed  
JTAG Mode  
Dedicated  
Flexible  
Dedicated  
Flexible  
TRST1  
LOW  
LOW  
HIGH  
HIGH  
PRA, PRB2  
User I/O3  
TDI, TCK, TDO2  
Probing Unavailable  
User I/O3  
No  
No  
No  
No  
Yes  
User I/O3  
Probe Circuit Outputs  
Probe Circuit Outputs  
Probe Circuit Secured  
Probe Circuit Inputs  
Probe Circuit Inputs  
Probe Circuit Secured  
Note:  
1. If the TRST pin is not reserved, the device behaves according to TRST=HIGH as described in the table.  
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input  
signals will not pass through these pins and may cause contention.  
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by  
the Designer software.  
SX-A Probe Circuit Control Pins  
Automotive-grade SX-A devices contain internal probing  
circuitry that provides built-in access to every node in a  
design, enabling 100% real-time observation and analysis  
of a device's internal logic nodes without design iteration.  
The probe circuitry is accessed by Silicon Explorer II, an  
easy-to-use integrated verification and logic analysis tool  
that can sample data at 100 MHz (asynchronous) or 66  
MHz (synchronous). Silicon Explorer II attaches to a PC's  
standard COM port, turning the PC into a fully functional  
18 channel logic analyzer. Silicon Explorer II allows  
designers to complete the design verification process at  
their desks and reduces verification time from several  
hours per cycle to a few seconds.  
The Silicon Explorer II tool uses the boundary-scan ports  
(TDI, TCK, TMS, and TDO) to select the desired nets for  
verification. The selected internal nets are assigned to  
the PRA/PRB pins for observation. Figure 1-11 illustrates  
the interconnection between Silicon Explorer II and the  
FPGA to perform in-circuit verification  
16 Pin  
Connection  
SX-A FPGAs  
TDI  
TCK  
TMS  
TDO  
Serial  
Silicon Explorer II  
Connection  
PRA  
PRB  
22 Pin  
Connection  
Additional 16 Channels  
(Logic Analyzer)  
Figure 1-11 Probe Setup  
1-10  
v2.2  
Design Considerations  
Programming  
Avoid using the TDI, TCK, TDO, PRA, and PRB pins as  
input or bidirectional ports. Since these pins are active  
during probing, critical input signals through these pins  
are not available. In addition, do not program the  
Security Fuse. Programming the Security Fuse disables  
the Probe Circuit. Actel recommends that you use a 70Ω  
series termination resistor on every probe connector  
(TDI, TCK, TMS, TDO, PRA, PRB). The 70series  
termination, effective for traces of fewer than 8 inches, is  
used to prevent data transmission corruption during  
probing and reading back the checksum.  
Device programming is supported through Silicon  
Sculptor series of programmers. In particular, Silicon  
Sculptor is compact, robust, single-site and multi-site  
device programmer for the PC.  
With standalone software, Silicon Sculptor  
allows  
concurrent programming of multiple units from the  
same PC, ensuring the fastest programming times  
possible. Each fuse is subsequently verified by Silicon  
Sculptor II to insure correct programming. In addition,  
integrity tests ensure that no extra fuses are  
programmed. Silicon Sculptor also provides extensive  
hardware self-testing capability.  
The procedure for programming an SX-A Automotive  
device using Silicon Sculptor is as follows:  
Development Tool Support  
The SX-A Automotive family of FPGAs is fully supported  
by both Actel's Libero® Integrated Design Environment  
and Designer FPGA Development software. Actel Libero  
1. Load the .AFM file  
2. Select the device to be programmed  
3. Begin programming  
IDE is  
a
design management environment that  
streamlines the design flow. Libero IDE provides an  
integrated design manager that seamlessly integrates  
design tools while guiding the user through the design  
flow, managing all design and log files, and passing  
necessary design data among tools. Additionally, Libero  
IDE allows users to integrate both schematic and HDL  
synthesis into a single flow and verify the entire design  
in a single environment. Libero IDE includes Synplify®  
for Actel from Synplicity®, ViewDraw® for Actel from  
Mentor Graphics®, ModelSim™ HDL Simulator from  
When the design is ready to go to production, Actel  
offers device volume-programming services either  
through distribution partners or via in-house  
programming from the factory.  
For detailed information on programming, read the  
following documents Programming Antifuse Devices and  
Silicon Sculptor User’s Guide.  
Mentor  
Graphics,  
WaveFormer  
Lite™  
from  
SynaptiCAD™, and Designer software from Actel. Refer  
to the Libero IDE flow (located on Actel’s website)  
diagram for more information.  
Actel's Designer software is a place-and-route tool and  
provides a comprehensive suite of backend support tools  
for FPGA development. The Designer software includes  
timing-driven place-and-route, and  
a
world-class  
integrated static timing analyzer and constraints editor.  
With the Designer software, a user can lock his/her  
design pins before layout while minimally impacting the  
results of place-and-route. Additionally, the back-  
annotation flow is compatible with all the major  
simulators and the simulation results can be cross-probed  
with Silicon Explorer II, Actel’s integrated verification  
and logic analysis tool. Another tool included in the  
Designer software is the SmartGen core generator, which  
easily creates popular and commonly used logic  
functions for implementation into your schematic or HDL  
design. Actel's Designer software is compatible with the  
most popular FPGA design entry and verification tools  
from companies such as Mentor Graphics, Synplicity,  
Synopsys, and Cadence Design Systems. The Designer  
software is available for both the Windows and UNIX  
operating systems.  
v2.2  
1-11  
Related Documents  
Application Notes  
Global Clock Networks in Actel’s Antifuse Devices  
http://www.actel.com/documents/GlobalClk_AN.pdf  
Using A54SX72A and RT54SX72S Quadrant Clocks  
http://www.actel.com/documents/QCLK_AN.pdf  
Implementation of Security in Actel Antifuse FPGAs  
http://www.actel.com/documents/  
Antifuse_Security_AN.pdf  
Actel eX, SX-A, and RTSX-S I/Os  
http://www.actel.com/documents/AntifuseIO_AN.pdf  
Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-  
Sparing Applications  
http://www.actel.com/documents/  
HotSwapColdSparing_AN.pdf  
Programming Antifuse Devices  
http://www.actel.com/documents/  
AntifuseProgram_AN.pdf  
Datasheets  
SX-A Family FPGAs  
http://www.actel.com/documents/SXA_DS.pdf  
HiRel SX-A Family FPGAs  
http://www.actel.com/documents/HRSXA_DS.pdf  
User’s Guides  
Silicon Sculptor User’s Guide  
http://www.actel.com/documents/SiliSculptII_WIN_ug.pdf  
1-12  
v2.2  
Operating Conditions  
Table 1-7 Absolute Maximum Ratings1  
Symbol  
VCCI  
Parameter  
Limits  
–0.3 to +4.0  
–0.3 to +3.0  
–0.5 to VCCI +0.5  
–0.5 to +VCCI  
–65 to +150  
Units  
DC Supply Voltage for I/Os  
DC Supply Voltage for Array  
Input Voltage  
V
V
VCCA  
VI  
V
VO  
Output Voltage  
V
TSTG  
Storage Temperature  
°C  
Notes:  
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute  
maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the  
Recommended Operating Conditions.  
2. SX-A Automotive devices are not 5 V tolerant.  
Table 1-8 Recommended Operating Conditions  
Parameter  
Automotive1  
–40 to +125  
Units  
Temperature Range2  
2.5V Power Supply Range  
3.3V Power Supply Range  
Notes:  
°C  
V
2.375 to 2.625  
3.135 to 3.465  
V
1. Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based on  
characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If testing to  
ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to discuss testing  
options available.  
2. Ambient temperature (TA).  
3.3V LVTTL Electrical Specifications  
Automotive  
Units  
Symbol  
Parameter  
Min  
Max  
VOH  
VCCI = MIN,  
VI = VIH or VIL  
IOH = –2mA  
IOL = 2mA  
2.4  
V
V
VOL  
VCCI = MIN,  
VI = VIH or VIL  
0.4  
0.7  
VIL  
Input Low Voltage  
Input High Voltage  
V
V
VIH  
2.1  
–20  
–20  
IIL / IIH  
IOZ  
Input Leakage Current, VIN = VCCI or GND  
3-State Output Leakage Current  
Input Transition Time tR, tF  
I/O Capacitance  
20  
20  
10  
10  
45  
µA  
µA  
ns  
1,2  
tR, tF  
CIO  
pF  
mA  
3
ICC  
Standby Current  
IV Curve  
Can be derived from the IBIS model at http://www.actel.com/techdocs/models/ibis.html.  
Note:  
1. tR is the transition time from 0.7V to 2.1V.  
2. tF is he transition time from 2.1V to 0.7V.  
3. ICC = ICCI + ICCA  
v2.2  
1-13  
2.5V LVCMOS2 Electrical Specifications  
Automotive  
Min. Max.  
Symbol  
Parameter  
Units  
VOH  
VCCI = MIN,  
VI = VIH or VIL  
IOH = -1mA  
IOL = 1mA  
1.8  
V
VOL  
VCCI = MIN,  
VI = VIH or VIL  
0.5  
0.6  
V
VIL  
Input Low Voltage, VOUT =< VVOL (max)  
Input High Voltage, VOUT >= VVOH (min)  
Input Leakage Current, VIN = VCCI or GND  
3-State Output Leakage Current  
Input Transition Time tR, tF  
V
V
VIH  
1.7  
–20  
–20  
IIL / IIH  
IOZ  
20  
20  
10  
10  
35  
µA  
µA  
ns  
1,2  
tR, tF  
CIO  
I/O Capacitance  
pF  
mA  
3
ICC  
Standby Current  
IV Curve  
Can be derived from the IBIS model at http://www.actel.com/techdocs/models/ibis.html.  
Note:  
1. tR is the transition time from 0.6V to 1.7V.  
2. tF is he transition time from 1.7V to 0.6V.  
3. ICC = ICCI + ICCA  
PCI Compliance for the Automotive-Grade SX-A Family  
The automotive-grade SX-A devices support 3.3V PCI and are compliant with the PCI Local Bus Specification Rev. 2.1.  
Table 1-9 DC Specifications (3.3V PCI Operation)  
Symbol  
VCCA  
VCCI  
VIH  
Parameter  
Condition  
Min.  
2.375  
3.135  
0.5VCCI  
–0.5  
Max.  
2.625  
Units  
V
Supply Voltage for Array  
Supply Voltage for I/Os  
Input High Voltage  
Input Low Voltage  
3.465  
V
VCCI + 0.5  
0.3VCCI  
V
VIL  
V
IIPU  
Input Pull-up Voltage1  
Input Leakage Current2  
Output High Voltage  
Output Low Voltage  
Input Pin Capacitance3  
CLK Pin Capacitance  
0.7VCCI  
–20  
V
IIL  
0 < VIN < VCCI  
IOUT = –500 µA  
IOUT = 1500 µA  
+20  
µA  
V
VOH  
VOL  
0.9VCCI  
0.1VCCI  
10  
V
CIN  
pF  
pF  
CCLK  
Note:  
5
12  
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a  
floated network. Designers should ensure that the input buffer is conducting minimum current at this input voltage in applications  
sensitive to static power utilization.  
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.  
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).  
1-14  
v2.2  
Table 1-10 AC Specifications (3.3V PCI Operation)  
Symbol  
Parameter  
Condition  
Min.  
–12VCCI  
Max.  
Units  
mA  
1
IOH(AC)  
Switching Current High  
0 < VOUT 0.3VCCI  
1
0.3VCCI VOUT < 0.9VCCI  
(–17.1(VCCI – VOUT))  
mA  
1, 2  
0.7VCCI < VOUT < VCCI  
EQ 1-1 on  
page 1-17  
2
(Test Point)  
V
OUT = 0.7VCC  
–32VCCI  
mA  
mA  
mA  
1
IOL(AC)  
Switching Current Low  
VCCI > VOUT 0.6VCCI  
16VCCI  
1
0.6VCCI > VOUT > 0.1VCCI  
0.18VCCI > VOUT > 0 1, 2  
(26.7VOUT)  
EQ 1-2 on  
page 1-17  
2
(Test Point)  
VOUT = 0.18VCC  
38VCCI  
mA  
mA  
ICL  
Low Clamp Current  
High Clamp Current  
Output Rise Slew Rate  
Output Fall Slew Rate  
–3 < VIN –1  
–25 + (VIN + 1)/0.015  
ICH  
VCCI + 4 > VIN VCCI + 1  
0.2VCCI - 0.6VCCI load 3  
0.6VCCI - 0.2VCCI load 3  
25 + (VIN – VCCI – 1)/0.015  
mA  
slewR  
slewF  
Note:  
1
1
4
4
V/ns  
V/ns  
1. Refer to the V/I curves in Figure 1-12 on page 1-16. Switching current characteristics for REQ# and GNT# are permitted to be one  
half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and  
RST#, which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and  
INTD#, which are open drain outputs.  
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C  
and D) are provided with the respective diagrams in Figure 1-12 on page 1-16. The equation defined maximum should be met by  
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.  
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any  
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter  
with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and  
minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain  
outputs.  
pin  
1/2 in. max.  
output  
buffer  
10 pF  
1k/25  
pin  
1k/25Ω  
output  
buffer  
10 pF  
v2.2  
1-15  
Figure 1-12 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the automotive-  
grade SX-A devices.  
150.0  
I
MAX Spec  
OL  
I
OL  
100.0  
50.0  
I
MIN Spec  
2.5  
OL  
0.0  
0
0.5  
MIN Spec  
1
1.5  
2
3
3.5  
4
–50.0  
–100.0  
–150.0  
I
OH  
I
MAX Spec  
I
OH  
OH  
Voltage Out (V)  
Figure 1-12 3.3V PCI V/I Curve for Automotive-Grade SX-A Devices  
Equation C  
IOH = (98.0/VCCI ) (VOUT – VCCI ) (VOUT + 0.4VCCI  
for 0.7 VCCI < VOUT < VCCI  
)
Equation D  
IOL = (256/VCCI ) VOUT (VCCI – VOUT  
for 0V < VOUT < 0.18 VCCI  
)
1-16  
v2.2  
Where:  
Junction Temperature (T )  
J
Ta = Ambient Temperature  
The temperature variable in the Designer Series software  
refers to the junction temperature, not the ambient  
temperature. This is an important distinction because the  
heat generated from dynamic power consumption is  
usually hotter than the ambient temperature.  
Equation 1, shown below, can be used to calculate  
junction temperature.  
T = Temperature gradient between junction (silicon)  
and ambient  
T = θ * P  
ja  
EQ 1-2  
P = Power  
= Junction to ambient of package. θ numbers are  
θ
Junction Temperature = T + Ta +  
ja  
ja  
located in the Package Thermal Characteristics table  
below.  
EQ 1-1  
Package Thermal Characteristics  
The device junction-to-case thermal characteristic is θjc,  
and the junction-to-ambient air characteristic is θja. The  
thermal characteristics for θja are shown with two  
different air flow rates.  
The maximum junction temperature is 150°C.  
A sample calculation of the absolute maximum power  
dissipation allowed for a TQFP 144-pin package at  
automotive temperature and still air is as follows:  
Max. junction temp. (°C) Max. ambient temp. (°C)  
150°C 125°C  
---------------------------------------------------------------------------------------------------------------------------------------  
Maximum Power Allowed =  
= --------------------------------------- = 0.78W  
θja(°C/W)  
32°C/W  
Table 1-11 Package Thermal Characteristics  
θja  
θja  
Package Type  
Pin Count  
100  
θjc  
12  
11  
8
Still Air  
300 ft/min  
Units  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Thin Quad Flat Pack (TQFP)  
37.5  
32  
30  
24  
Thin Quad Flat Pack (TQFP)  
144  
Plastic Quad Flat Pack (PQFP)1  
Plastic Quad Flat Pack (PQFP) with Heat Spreader2  
Fine Pitch Ball Grid Array (FBGA)  
Fine Pitch Ball Grid Array (FBGA)  
Fine Pitch Ball Grid Array (FBGA)  
208  
30  
23  
208  
3.8  
3.8  
3.3  
3
20  
17  
144  
38.8  
30  
26.7  
25  
256  
484  
20  
15  
Note:  
1. The A54SX08A PQ208 has no heat spreader.  
2. The SX-A PQ208 package has a heat spreader for A54SX16A, A54SX32A, and A54SX72A.  
For Power Estimator information, please go to http://www.actel.com/products/tools/index.html.  
v2.2  
1-17  
SX-A Timing Model*  
Input Delays  
Internal Delays  
Predicted  
Routing  
Delays  
Output Delays  
Combinatorial  
Cell  
t
= 0.5 ns  
= 0.7 ns  
I/O Module  
I/O Module  
IRD1  
t
= 1.0 ns  
t
INYH  
IRD2  
t
= 3.8 ns  
t
= 1.5 ns  
DHL  
PD  
t
= 0.6 ns  
= 1.1 ns  
= 2.0 ns  
RD1  
t
RD4  
t
RD8  
I/O Module  
t
= 3.8 ns  
Register  
Cell  
DHL  
D
Q
t
t
RD1  
= 1.2 ns  
= 0.0 ns  
= 0.6 ns  
SUD  
t
HD  
t
t
= 2.8 ns  
ENZL  
Routed  
Clock  
t
= 2.2 ns  
RCKH  
t
= 1.0 ns  
(100% Load)  
RCO  
I/O Module  
= 3.8 ns  
Register  
Cell  
DHL  
I/O Module  
t
= 1.0 ns  
INYH  
D
Q
t
t
RD1  
= 1.2 ns  
= 0.6 ns  
SUD  
t
= 0.0 ns  
HD  
t
ENZL  
= 2.8 ns  
Hard-Wired  
Clock  
t
t
RCO  
= 1.8 ns  
= 1.0 ns  
HCKH  
Note: *Values shown for A54SX08A, worst-case automotive conditions at 3.3V PCI with standard place-and-route.  
Figure 1-13 Timing Model  
Sample Path Calculations  
Hardwired Clock  
Routed Clock  
External Setup =(tINYH + tIRD2 + tSUD) – tHCKH  
External Setup = (tINYH + tIRD2 + tSUD) – tRCKH  
=1.0+0.7+1.2-1.8=1.1ns  
Clock-to-Out (Pad-to-Pad)  
= 1.0+0.7+1.2-1.8=1.1ns  
Clock-to-Out (Pad-to-Pad)  
=tHCKH + tRCO + tRD1 + tDHL  
=1.8+1.0+0.6+3.8=7.2ns  
= tRCKH + tRCO + tRD1 + tDHL  
=
1.8+1.0+0.6+3.8=7.2ns  
1-18  
v2.2  
Output Buffer Delays  
E
D
PAD  
To AC test loads (shown below)  
TRIBUFF  
VCC  
VCC  
VCC  
In  
GND  
1.5V  
GND  
10%  
50% 50%  
VOH  
En  
E
GND  
90%  
50% 50%  
50% 50%  
VOH  
VCC  
1.5V  
VOL  
Out  
VOL  
Out  
Out  
GND  
1.5V  
1.5V  
tDLH  
tDHL  
tENZL  
tENLZ  
tENZH  
tENHZ  
Figure 1-14 Output Buffer Delay  
Load 2  
(Used to measure enable delays)  
Load 3  
(Used to measure disable delays)  
Load 1  
(Used to measure  
propagation delay)  
VCC  
VCC  
GND  
GND  
To the output  
under test  
R toVCC for tPZL  
R toVCC for tPLZ  
35 pF  
R to GND for tPZH  
R to GND for tPHZ  
To the output  
under test  
To the output  
under test  
R = 1 k  
R = 1 k  
35 pF  
5 pF  
Figure 1-15 AC Test Loads  
S
Y
A
B
Y
PAD  
INBUF  
VCC  
S, A or B  
GND  
50%  
50%  
50%  
VCC  
3V  
Out  
GND  
In  
0V  
50%  
1.5V 1.5V  
VCC  
tPD  
tPD  
50%  
VCC  
Out  
GND  
Out  
50%  
GND  
50%  
tPD  
50%  
tPD  
Figure 1-16 Input Buffer Delays  
Figure 1-17 C-Cell Delays  
v2.2  
1-19  
Cell Timing Characteristics  
D
PRESET  
CLR  
Q
CLK  
(Positive Edge-Triggered)  
tHD  
D
tHP  
tSUD  
tHPWH  
tRPWH  
CLK  
t HPWL  
t RPWL  
tRCO  
Q
tCLR  
tPRESET  
CLR  
tWASYN  
PRESET  
Figure 1-18 Cell Timing Characteristics  
Long Tracks  
Timing Characteristics  
Some nets in the design use long tracks. Long tracks are  
special routing resources that span multiple rows,  
columns, or modules. Long tracks employ three to five  
antifuse connections. This increases capacitance and  
resistance, resulting in longer net delays for macros  
connected to long tracks. Typically, up to 6 percent of  
nets in a fully utilized device require long tracks. Long  
tracks contribute approximately 4 ns to 8.4 ns delay. This  
additional delay is represented statistically in higher  
fanout routing delays.  
Timing characteristics for SX-A devices fall into three  
categories: family-dependent, device-dependent, and  
design-dependent. The input and output buffer  
characteristics are common to all SX-A family members.  
Internal routing delays are device-dependent. Design  
dependency means actual delays are not determined  
until after placement and routing of the user’s design are  
complete. Delay values may then be determined by using  
the Timer utility or performing simulation with post-  
layout delays.  
Timing Derating  
Critical Nets and Typical Nets  
SX-A devices are manufactured with a CMOS process.  
Therefore, device performance varies according to  
temperature, voltage, and process changes. Minimum  
timing parameters reflect maximum operating voltage,  
minimum operating temperature, and best-case  
processing. Maximum timing parameters reflect  
minimum operating voltage, maximum operating  
temperature, and worst-case processing.  
Propagation delays are expressed only for typical nets,  
which are used for initial design performance evaluation.  
Critical net delays can then be applied to the most timing  
critical paths. Critical nets are determined by net  
property assignment prior to placement and routing. Up  
to 6 percent of the nets in a design may be designated as  
critical, while 90 percent of the nets in a design are  
typical.  
1-20  
v2.2  
Table 1-12 Temperature and Voltage Derating Factors  
(Normalized to TJ = 125°C, VCCA = 2.3 V)  
Junction Temperature (TJ)  
VCCA  
2.3 V  
2.5 V  
2.7 V  
–55°C  
0.7  
–40°C  
0.70  
0°C  
25°C  
0.78  
0.73  
0.69  
70°C  
85°C  
0.91  
0.85  
0.80  
125°C  
1.00  
0.77  
0.72  
0.67  
0.88  
0.83  
0.78  
0.65  
0.66  
0.66  
0.93  
0.62  
0.88  
Table 1-13 A54SX08A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C)  
‘Std’ Speed  
Parameter  
Description  
Min.  
Max.  
Units  
C-Cell Propagation Delays1  
tPD  
Internal Array Module  
1.5  
ns  
Predicted Routing Delays2  
tDC  
FO=1 Routing Delay, Direct Connect  
0.1  
0.5  
0.6  
0.7  
0.9  
1.1  
2.0  
2.9  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tFC  
FO=1 Routing Delay, Fast Connect  
FO=1 Routing Delay  
tRD1  
tRD2  
FO=2 Routing Delay  
tRD3  
FO=3 Routing Delay  
tRD4  
FO=4 Routing Delay  
tRD8  
FO=8 Routing Delay  
tRD12  
R-Cell Timing  
tRCO  
FO=12 Routing Delay  
Sequential Clock-to-Q  
1.0  
1.2  
1.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCLR  
Asynchronous Clear-to-Q  
Asynchronous Preset-to-Q  
Flip-Flop Data Input Set-Up  
Flip-Flop Data Input Hold  
Asynchronous Pulse Width  
Asynchronous Recovery Time  
Asynchronous Hold Time  
tPRESET  
tSUD  
1.2  
0.0  
2.3  
0.6  
0.5  
tHD  
tWASYN  
tRECASYN  
tHASYN  
Input Module Propagation Delays  
tINYH  
Input Data Pad-to-Y HIGH  
Input Data Pad-to-Y LOW  
1.0  
1.6  
ns  
ns  
tINYL  
Notes:  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
v2.2  
1-21  
Table 1-13 A54SX08A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)  
‘Std’ Speed  
Parameter  
Description  
Min.  
Max.  
Units  
Input Module Predicted Routing Delays2  
tIRD1  
tIRD2  
tIRD3  
tIRD4  
tIRD8  
tIRD12  
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
FO=12 Routing Delay  
0.5  
0.7  
0.9  
1.1  
2.0  
2.9  
ns  
ns  
ns  
ns  
ns  
ns  
Dedicated (Hardwired) Array Clock Networks  
tHCKH  
Input LOW to HIGH  
(Pad to R-Cell Input)  
2.1  
1.8  
ns  
tHCKL  
Input HIGH to LOW  
(Pad to R-Cell Input)  
ns  
ns  
tHPWH  
tHPWL  
tHCKSW  
tHP  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
2.4  
2.4  
ns  
0.3  
ns  
Minimum Period  
4.8  
ns  
fHMAX  
Maximum Frequency  
208  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (Light Load)  
(Pad to R-Cell Input)  
1.8  
2.2  
2.2  
2.5  
2.3  
2.6  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (Light Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (50% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (50% Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (100% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (100% Load)  
(Pad to R-Cell Input)  
ns  
ns  
ns  
ns  
ns  
ns  
tRPWH  
Min. Pulse Width HIGH  
2.4  
2.4  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Notes:  
Maximum Skew (Light Load)  
Maximum Skew (50% Load)  
Maximum Skew (100% Load)  
0.3  
0.5  
0.5  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
1-22  
v2.2  
Table 1-13 A54SX08A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)  
‘Std’ Speed  
Parameter  
Description  
Min.  
Max.  
Units  
Dedicated (Hardwired) Array Clock Networks  
tHCKH  
tHCKL  
Input LOW to HIGH  
(Pad to R-Cell Input)  
1.8  
ns  
Input HIGH to LOW  
(Pad to R-Cell Input)  
1.7  
ns  
ns  
tHPWH  
tHPWL  
tHCKSW  
tHP  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
2.4  
2.4  
ns  
0.3  
ns  
Minimum Period  
4.8  
ns  
fHMAX  
Maximum Frequency  
208  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (Light Load)  
(Pad to R-Cell Input)  
1.8  
2.3  
2.1  
2.5  
2.2  
2.6  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (Light Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (50% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (50% Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (100% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (100% Load)  
(Pad to R-Cell Input)  
ns  
ns  
ns  
ns  
ns  
ns  
tRPWH  
Min. Pulse Width HIGH  
2.4  
2.4  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Maximum Skew (Light Load)  
Maximum Skew (50% Load)  
Maximum Skew (100% Load)  
0.5  
0.5  
0.5  
2.5 V LVTTL Output Module Timing3  
tDLH  
Data-to-Pad LOW to HIGH  
5.0  
21.8  
4.6  
ns  
ns  
ns  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Data-to-Pad HIGH to LOW—low slew  
Enable-to-Pad, Z to L  
tDHLS  
tENZL  
tENZLS  
Notes:  
22.8  
6.7  
Data-to-Pad, Z to L—low slew  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
v2.2  
1-23  
Table 1-13 A54SX08A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)  
‘Std’ Speed  
Parameter  
tENZH  
Description  
Min.  
Max.  
4.1  
Units  
ns  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
Enable-to-Pad, H to Z  
Delta LOW to HIGH  
Delta HIGH to LOW  
Delta HIGH to LOW—low slew  
tENLZ  
6.7  
ns  
tENHZ  
0.064  
0.029  
0.108  
5.0  
ns  
dTLH  
ns/pF  
ns/pF  
ns/pF  
dTHL  
dTHLS  
3.3 V PCI Output Module Timing4  
tDLH  
Data-to-Pad LOW to HIGH  
3.8  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Enable-to-Pad, Z to L  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
Enable-to-Pad, H to Z  
Delta LOW to HIGH  
Delta HIGH to LOW  
3.8  
2.8  
tENZL  
tENZH  
tENLZ  
tENHZ  
dTLH  
dTHL  
ns  
2.8  
ns  
4.8  
ns  
4.8  
ns  
0.050  
0.019  
ns/pF  
ns/pF  
3.3 V LVTTL Output Module Timing3  
tDLH  
Data-to-Pad LOW to HIGH  
5.3  
4.8  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Data-to-Pad HIGH to LOW—low slew  
Enable-to-Pad, Z to L  
tDHLS  
tENZL  
tENZLS  
tENZH  
tENLZ  
tENHZ  
dTLH  
17.3  
4.3  
ns  
ns  
Enable-to-Pad, Z to L—low slew  
Enable-to-Pad, Z to H  
31.9  
5.5  
ns  
ns  
Enable-to-Pad, L to Z  
5.5  
ns  
Enable-to-Pad, H to Z  
4.8  
ns  
Delta LOW to HIGH  
0.050  
0.019  
0.092  
ns/pF  
ns/pF  
ns/pF  
dTHL  
Delta HIGH to LOW  
dTHLS  
Notes:  
Delta HIGH to LOW—low slew  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
1-24  
v2.2  
Table 1-14 A54SX16A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125°C)  
‘Std’ Speed  
Min Max.  
Parameter  
Description  
Units  
C-Cell Propagation Delays1  
tPD  
Internal Array Module  
1.5  
ns  
Predicted Routing Delays2  
tDC  
FO=1 Routing Delay, Direct Connect  
0.1  
0.5  
0.6  
0.7  
0.9  
1.1  
2.0  
2.9  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tFC  
FO=1 Routing Delay, Fast Connect  
FO=1 Routing Delay  
tRD1  
tRD2  
FO=2 Routing Delay  
tRD3  
FO=3 Routing Delay  
tRD4  
FO=4 Routing Delay  
tRD8  
FO=8 Routing Delay  
tRD12  
R-Cell Timing  
tRCO  
FO=12 Routing Delay  
Sequential Clock-to-Q  
1.0  
1.2  
1.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCLR  
Asynchronous Clear-to-Q  
Asynchronous Preset-to-Q  
Flip-Flop Data Input Set-Up  
Flip-Flop Data Input Hold  
Asynchronous Pulse Width  
Asynchronous Recovery Time  
Asynchronous Removal Time  
tPRESET  
tSUD  
1.2  
0.0  
2.3  
0.6  
0.5  
tHD  
tWASYN  
tRECASYN  
tHASYN  
Input Module Propagation Delays  
tINYH Input Data Pad-to-Y HIGH  
tINYL Input Data Pad-to-Y LOW  
Input Module Predicted Routing Delays2  
1.0  
1.6  
ns  
ns  
tIRD1  
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
FO=12 Routing Delay  
0.5  
0.7  
0.9  
1.1  
0.9  
2.9  
ns  
ns  
ns  
ns  
ns  
ns  
tIRD2  
tIRD3  
tIRD4  
tIRD8  
tIRD12  
Notes:  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
v2.2  
1-25  
Table 1-14 A54SX16A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125°C) (Continued)  
‘Std’ Speed  
Parameter  
Description  
Min  
Max.  
Units  
Dedicated (Hardwired) Array Clock Networks  
tHCKH  
tHCKL  
Input LOW to HIGH  
(Pad to R-Cell Input)  
2.2  
2.1  
ns  
Input HIGH to LOW  
(Pad to R-Cell Input)  
ns  
ns  
tHPWH  
tHPWL  
tHCKSW  
tHP  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
2.4  
2.4  
ns  
0.1  
ns  
Minimum Period  
4.8  
ns  
fHMAX  
Maximum Frequency  
208  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (Light Load)  
(Pad to R-Cell Input)  
2.1  
2.2  
2.6  
2.4  
2.6  
3.1  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (Light Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (50% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (50% Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (100% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (100% Load)  
(Pad to R-Cell Input)  
ns  
ns  
ns  
ns  
ns  
ns  
tRPWH  
Min. Pulse Width HIGH  
2.4  
2.4  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Maximum Skew (Light Load)  
Maximum Skew (50% Load)  
Maximum Skew (100% Load)  
0.5  
0.9  
0.9  
Dedicated (Hardwired) Array Clock Networks  
tHCKH  
Input LOW to HIGH  
(Pad to R-Cell Input)  
2.2  
2.1  
ns  
ns  
tHCKL  
Input HIGH to LOW  
(Pad to R-Cell Input)  
Notes:  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
1-26  
v2.2  
Table 1-14 A54SX16A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125°C) (Continued)  
‘Std’ Speed  
Parameter  
tHPWH  
Description  
Min  
2.4  
Max.  
Units  
ns  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
tHPWL  
2.4  
ns  
tHCKSW  
tHP  
0.1  
ns  
Minimum Period  
4.8  
ns  
fHMAX  
Maximum Frequency  
208  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (Light Load)  
(Pad to R-Cell Input)  
2.1  
2.3  
2.6  
2.7  
3.0  
3.1  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (Light Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (50% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (50% Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (100% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (100% Load)  
(Pad to R-Cell Input)  
ns  
ns  
ns  
ns  
ns  
ns  
tRPWH  
Min. Pulse Width HIGH  
2.4  
2.4  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Maximum Skew (Light Load)  
Maximum Skew (50% Load)  
Maximum Skew (100% Load)  
0.5  
0.9  
0.9  
2.5 V LVTTL Output Module Timing3  
tDLH  
Data-to-Pad LOW to HIGH  
6.3  
5.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Data-to-Pad HIGH to LOW—low slew  
Enable-to-Pad, Z to L  
tDHLS  
tENZL  
tENZLS  
tENZH  
tENLZ  
tENHZ  
Notes:  
21.8  
4.6  
Data-to-Pad, Z to L—low slew  
Enable-to-Pad, Z to H  
22.8  
6.7  
Enable-to-Pad, L to Z  
4.1  
Enable-to-Pad, H to Z  
6.7  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
v2.2  
1-27  
Table 1-14 A54SX16A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125°C) (Continued)  
‘Std’ Speed  
Parameter  
dTLH  
Description  
Min  
Max.  
0.064  
0.029  
0.108  
Units  
ns/pF  
ns/pF  
ns/pF  
Delta LOW to HIGH  
Delta HIGH to LOW  
Delta HIGH to LOW—low slew  
dTHL  
dTHLS  
3.3 V PCI Output Module Timing4  
tDLH  
Data-to-Pad LOW to HIGH  
3.8  
3.8  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Enable-to-Pad, Z to L  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
Enable-to-Pad, H to Z  
Delta LOW to HIGH  
Delta HIGH to LOW  
tENZL  
tENZH  
tENLZ  
tENHZ  
dTLH  
dTHL  
2.8  
ns  
2.8  
ns  
4.8  
ns  
4.8  
ns  
0.050  
0.019  
ns/pF  
ns/pF  
3.3 V LVTTL Output Module Timing3  
tDLH  
Data-to-Pad LOW to HIGH  
5.3  
4.8  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Data-to-Pad HIGH to LOW—low slew  
Enable-to-Pad, Z to L  
tDHLS  
tENZL  
tENZLS  
tENZH  
tENLZ  
tENHZ  
dTLH  
17.3  
4.3  
ns  
ns  
Enable-to-Pad, Z to L—low slew  
Enable-to-Pad, Z to H  
31.9  
5.5  
ns  
ns  
Enable-to-Pad, L to Z  
5.5  
ns  
Enable-to-Pad, H to Z  
4.8  
ns  
Delta LOW to HIGH  
0.050  
0.019  
0.092  
ns/pF  
ns/pF  
ns/pF  
dTHL  
Delta HIGH to LOW  
dTHLS  
Notes:  
Delta HIGH to LOW—low slew  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
1-28  
v2.2  
Table 1-15 A54SX32A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C  
‘Std’ Speed  
Parameter  
Description  
Min.  
Max.  
Units  
C-Cell Propagation Delays1  
tPD  
Internal Array Module  
1.5  
ns  
Predicted Routing Delays2  
tDC  
FO=1 Routing Delay, Direct Connect  
0.1  
0.5  
0.6  
0.7  
0.9  
1.1  
2.0  
2.9  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tFC  
FO=1 Routing Delay, Fast Connect  
FO=1 Routing Delay  
tRD1  
tRD2  
FO=2 Routing Delay  
tRD3  
FO=3 Routing Delay  
tRD4  
FO=4 Routing Delay  
tRD8  
FO=8 Routing Delay  
tRD12  
R-Cell Timing  
tRCO  
FO=12 Routing Delay  
Sequential Clock-to-Q  
1.0  
1.2  
1.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCLR  
Asynchronous Clear-to-Q  
Asynchronous Preset-to-Q  
Flip-Flop Data Input Set-Up  
Flip-Flop Data Input Hold  
Asynchronous Pulse Width  
Asynchronous Recovery Time  
Asynchronous Removal Time  
tPRESET  
tSUD  
1.2  
0.0  
2.3  
0.6  
0.5  
tHD  
tWASYN  
tRECASYN  
tHASYN  
Input Module Propagation Delays  
tINYH Input Data Pad-to-Y HIGH  
tINYL Input Data Pad-to-Y LOW  
Input Module Predicted Routing Delays2  
1.0  
1.6  
ns  
ns  
tIRD1  
FO=1 Routing Delay  
FO=2 Routing Delay  
0.5  
0.7  
ns  
ns  
tIRD2  
Notes:  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
v2.2  
1-29  
Table 1-15 A54SX32A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C (Continued)  
‘Std’ Speed  
Parameter  
tIRD3  
Description  
Min.  
Max.  
0.9  
Units  
ns  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
FO=12 Routing Delay  
tIRD4  
1.1  
ns  
tIRD8  
2.0  
ns  
tIRD12  
2.9  
ns  
Dedicated (Hardwired) Array Clock Networks  
tHCKH  
Input LOW to HIGH  
(Pad to R-Cell Input)  
3.1  
ns  
ns  
tHCKL  
Input HIGH to LOW  
(Pad to R-Cell Input)  
2.6  
tHPWH  
tHPWL  
tHCKSW  
tHP  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
2.5  
2.5  
ns  
ns  
0.6  
ns  
Minimum Period  
5.0  
ns  
fHMAX  
Maximum Frequency  
199  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (Light Load)  
(Pad to R-Cell Input)  
3.0  
3.7  
3.7  
3.9  
4.3  
4.3  
ns  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (Light Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (50% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (50% Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (100% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (100% Load)  
(Pad to R-Cell Input)  
tRPWH  
Min. Pulse Width HIGH  
2.5  
2.5  
ns  
ns  
ns  
ns  
ns  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Notes:  
Maximum Skew (Light Load)  
Maximum Skew (50% Load)  
Maximum Skew (100% Load)  
1.5  
2.2  
2.3  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
1-30  
v2.2  
Table 1-15 A54SX32A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C (Continued)  
‘Std’ Speed  
Parameter  
Description  
Min.  
Max.  
Units  
Dedicated (Hardwired) Array Clock Networks  
tHCKH  
tHCKL  
Input LOW to HIGH  
(Pad to R-Cell Input)  
3.1  
ns  
ns  
Input HIGH to LOW  
(Pad to R-Cell Input)  
2.6  
tHPWH  
tHPWL  
tHCKSW  
tHP  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
2.5  
2.5  
ns  
ns  
0.6  
ns  
Minimum Period  
5.0  
ns  
fHMAX  
Maximum Frequency  
199  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (Light Load)  
(Pad to R-Cell Input)  
3.0  
3.7  
3.7  
3.9  
4.3  
4.3  
ns  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (Light Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (50% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (50% Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (100% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (100% Load)  
(Pad to R-Cell Input)  
tRPWH  
Min. Pulse Width HIGH  
2.5  
2.5  
ns  
ns  
ns  
ns  
ns  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Maximum Skew (Light Load)  
Maximum Skew (50% Load)  
Maximum Skew (100% Load)  
1.5  
2.2  
2.3  
Dedicated (Hardwired) Array Clock Networks  
tHCKH  
Input LOW to HIGH  
(Pad to R-Cell Input)  
3.1  
2.6  
ns  
ns  
tHCKL  
Input HIGH to LOW  
(Pad to R-Cell Input)  
Notes:  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
v2.2  
1-31  
Table 1-15 A54SX32A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C (Continued)  
‘Std’ Speed  
Parameter  
tHPWH  
Description  
Min.  
2.5  
Max.  
Units  
ns  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
0.0  
tHPWL  
2.5  
ns  
tHCKSW  
tHP  
0.6  
ns  
Minimum Period  
5.0  
ns  
fHMAX  
Maximum Frequency  
199  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (Light Load)  
(Pad to R-Cell Input)  
3.0  
3.8  
3.7  
3.9  
4.3  
4.3  
ns  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (Light Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (50% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (50% Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (100% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (100% Load)  
(Pad to R-Cell Input)  
tRPWH  
Min. Pulse Width HIGH  
2.5  
2.5  
ns  
ns  
ns  
ns  
ns  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Maximum Skew (Light Load)  
Maximum Skew (50% Load)  
Maximum Skew (100% Load)  
1.5  
2.2  
2.3  
2.5 V LVTTL Output Module Timing3  
tDLH  
Data-to-Pad LOW to HIGH  
6.3  
5.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Data-to-Pad HIGH to LOW—low slew  
Enable-to-Pad, Z to L  
tDHLS  
tENZL  
tENZLS  
tENZH  
tENLZ  
tENHZ  
Notes:  
21.8  
4.6  
Data-to-Pad, Z to L—low slew  
Enable-to-Pad, Z to H  
22.8  
6.7  
Enable-to-Pad, L to Z  
4.1  
Enable-to-Pad, H to Z  
6.7  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
1-32  
v2.2  
Table 1-15 A54SX32A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C (Continued)  
‘Std’ Speed  
Parameter  
dTLH  
Description  
Min.  
Max.  
0.064  
0.029  
0.108  
Units  
ns/pF  
ns/pF  
ns/pF  
Delta LOW to HIGH  
Delta HIGH to LOW  
Delta HIGH to LOW—low slew  
dTHL  
dTHLS  
3.3 V PCI Output Module Timing4  
tDLH  
Data-to-Pad LOW to HIGH  
3.8  
3.8  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Enable-to-Pad, Z to L  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
Enable-to-Pad, H to Z  
Delta LOW to HIGH  
Delta HIGH to LOW  
tENZL  
tENZH  
tENLZ  
tENHZ  
dTLH  
dTHL  
2.8  
ns  
2.8  
ns  
4.8  
ns  
4.8  
ns  
0.050  
0.019  
ns/pF  
ns/pF  
3.3 V LVTTL Output Module Timing3  
tDLH  
Data-to-Pad LOW to HIGH  
5.3  
4.8  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Data-to-Pad HIGH to LOW—low slew  
Enable-to-Pad, Z to L  
tDHLS  
tENZL  
tENZLS  
tENZH  
tENLZ  
tENHZ  
dTLH  
17.3  
4.3  
ns  
ns  
Enable-to-Pad, Z to L—low slew  
Enable-to-Pad, Z to H  
31.9  
5.5  
ns  
ns  
Enable-to-Pad, L to Z  
5.5  
ns  
Enable-to-Pad, H to Z  
4.8  
ns  
Delta LOW to HIGH  
0.050  
0.019  
ns/pF  
ns/pF  
ns/pF  
dTHL  
Delta HIGH to LOW  
dTHLS  
Notes:  
Delta HIGH to LOW—low slew  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
v2.2  
1-33  
Table 1-16 A54SX72A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C)  
‘Std’ Speed  
Min. Max.  
Parameter  
Description  
Units  
C-Cell Propagation Delays1  
tPD  
Internal Array Module  
1.5  
ns  
Predicted Routing Delays2  
tDC  
FO=1 Routing Delay, Direct Connect  
0.1  
0.5  
0.6  
0.8  
1.0  
1.2  
2.4  
3.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tFC  
FO=1 Routing Delay, Fast Connect  
FO=1 Routing Delay  
tRD1  
tRD2  
FO=2 Routing Delay  
tRD3  
FO=3 Routing Delay  
tRD4  
FO=4 Routing Delay  
tRD8  
FO=8 Routing Delay  
tRD12  
R-Cell Timing  
tRCO  
FO=12 Routing Delay  
Sequential Clock-to-Q  
1.0  
1.2  
1.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCLR  
Asynchronous Clear-to-Q  
Asynchronous Preset-to-Q  
Flip-Flop Data Input Set-Up  
Flip-Flop Data Input Hold  
Asynchronous Pulse Width  
Asynchronous Recovery Time  
Asynchronous Hold Time  
tPRESET  
tSUD  
1.2  
0.0  
2.3  
0.6  
0.5  
tHD  
tWASYN  
tRECASYN  
tHASYN  
Input Module Propagation Delays  
tINYH Input Data Pad-to-Y HIGH  
tINYL Input Data Pad-to-Y LOW  
Input Module Predicted Routing Delays2  
1.0  
1.6  
ns  
ns  
tIRD1  
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
FO=12 Routing Delay  
0.6  
0.8  
1.0  
1.2  
2.4  
3.4  
ns  
ns  
ns  
ns  
ns  
ns  
tIRD2  
tIRD3  
tIRD4  
tIRD8  
tIRD12  
Notes:  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
1-34  
v2.2  
Table 1-16 A54SX72A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)  
‘Std’ Speed  
Parameter  
Description  
Min.  
Max.  
Units  
Dedicated (Hardwired) Array Clock Networks  
tHCKH  
tHCKL  
Input LOW to HIGH  
(Pad to R-Cell Input)  
2.4  
2.2  
ns  
ns  
Input HIGH to LOW  
(Pad to R-Cell Input)  
tHPWH  
tHPWL  
tHCKSW  
tHP  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
2.5  
2.5  
ns  
ns  
1.1  
199  
4.0  
ns  
Minimum Period  
5.0  
ns  
fHMAX  
Maximum Frequency  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (Light Load)  
(Pad to R-Cell Input)  
ns  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (Light Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (50% Load)  
(Pad to R-Cell Input)  
4.6  
5.3  
Input HIGH to LOW (50% Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (100% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (100% Load)  
(Pad to R-Cell Input)  
tRPWH  
Min. Pulse Width HIGH  
5.6  
6.5  
6.9  
ns  
ns  
ns  
ns  
ns  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Maximum Skew (Light Load)  
Maximum Skew (50% Load)  
Maximum Skew (100% Load)  
Dedicated (Hardwired) Array Clock Networks  
tHCKH  
Input LOW to HIGH  
(Pad to R-Cell Input)  
2.4  
2.2  
ns  
ns  
tHCKL  
Input HIGH to LOW  
(Pad to R-Cell Input)  
Notes:  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
v2.2  
1-35  
Table 1-16 A54SX72A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)  
‘Std’ Speed  
Parameter  
tHPWH  
Description  
Min.  
2.5  
Max.  
Units  
ns  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
tHPWL  
2.5  
ns  
tHCKSW  
tHP  
1.1  
199  
4.0  
ns  
Minimum Period  
5.0  
ns  
fHMAX  
Maximum Frequency  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (Light Load)  
(Pad to R-Cell Input)  
ns  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (Light Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (50% Load)  
(Pad to R-Cell Input)  
4.7  
5.3  
Input HIGH to LOW (50% Load)  
(Pad to R-Cell Input)  
Input LOW to HIGH (100% Load)  
(Pad to R-Cell Input)  
Input HIGH to LOW (100% Load)  
(Pad to R-Cell Input)  
tRPWH  
Min. Pulse Width HIGH  
5.6  
6.5  
6.9  
ns  
ns  
ns  
ns  
ns  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Maximum Skew (Light Load)  
Maximum Skew (50% Load)  
Maximum Skew (100% Load)  
2.5 V LVTTL Output Module Timing3  
tDLH  
Data-to-Pad LOW to HIGH  
6.5  
5.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Data-to-Pad HIGH to LOW—low slew  
Enable-to-Pad, Z to L  
tDHLS  
tENZL  
tENZLS  
tENZH  
tENLZ  
tENHZ  
Notes:  
22.6  
4.6  
Data-to-Pad, Z to L—low slew  
Enable-to-Pad, Z to H  
22.8  
6.7  
Enable-to-Pad, L to Z  
4.1  
Enable-to-Pad, H to Z  
6.7  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
1-36  
v2.2  
Table 1-16 A54SX72A Timing Characteristics  
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)  
‘Std’ Speed  
Parameter  
dTLH  
Description  
Min.  
Max.  
0.064  
0.029  
0.108  
Units  
ns/pF  
ns/pF  
ns/pF  
Delta LOW to HIGH  
Delta HIGH to LOW  
Delta HIGH to LOW—low slew  
dTHL  
dTHLS  
3.3 V PCI Output Module Timing4  
tDLH  
Data-to-Pad LOW to HIGH  
3.8  
3.8  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Enable-to-Pad, Z to L  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
Enable-to-Pad, H to Z  
Delta LOW to HIGH  
Delta HIGH to LOW  
tENZL  
tENZH  
tENLZ  
tENHZ  
dTLH  
dTHL  
2.8  
ns  
2.8  
ns  
4.8  
ns  
4.8  
ns  
0.050  
0.019  
ns/pF  
ns/pF  
3.3 V LVTTL Output Module Timing3  
tDLH  
Data-to-Pad LOW to HIGH  
5.3  
4.8  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Data-to-Pad HIGH to LOW—low slew  
Enable-to-Pad, Z to L  
tDHLS  
tENZL  
tENZLS  
tENZH  
tENLZ  
tENHZ  
dTLH  
17.3  
4.3  
ns  
ns  
Enable-to-Pad, Z to L—low slew  
Enable-to-Pad, Z to H  
31.9  
5.5  
ns  
ns  
Enable-to-Pad, L to Z  
5.5  
ns  
Enable-to-Pad, H to Z  
4.8  
ns  
Delta LOW to HIGH  
0.050  
0.019  
0.092  
ns/pF  
ns/pF  
ns/pF  
dTHL  
Delta HIGH to LOW  
dTHLS  
Notes:  
Delta HIGH to LOW—low slew  
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Delays based on 35 pF loading.  
4. Delays based on 10 pF loading and 25 resistance.  
v2.2  
1-37  
TCK, I/O  
Test Clock  
Pin Description  
Test clock input for diagnostic probe and device  
programming. In flexible mode, TCK becomes active  
when the TMS pin is set LOW (refer to Table 1-5 on  
page 1-9). This pin functions as an I/O when the  
boundary scan state machine reaches the “logic reset”  
state.  
CLKA/B  
Clock A and B  
These pins are clock inputs for clock distribution  
networks. Input levels are compatible with standard  
LVTTL or 3.3 V PCI specifications. The clock input is  
buffered prior to clocking the R-cells. If not used, these  
pins must be set LOW or HIGH on the board except  
A54SX72A. In A54SX72A these clocks can be configured  
as user I/O.  
TDI, I/O  
Test Data Input  
Serial input for boundary scan testing and diagnostic  
probe. In flexible mode, TDI is active when the TMS pin is  
set LOW (refer to Table 1-5 on page 1-9). This pin  
functions as an I/O when the boundary scan state  
machine reaches the “logic reset” state.  
QCLKA/B/C/D,  
Quadrant Clock A, B, C, and D  
I/O  
These four pins are the quadrant clock inputs and are  
only for A54SX72A with A, B, C and D corresponding to  
bottom-left, bottom-right, top-left and top-right  
quadrants, respectively. They are clock inputs for clock  
distribution networks. Input levels are compatible with  
standard LVTTL and 3.3 V PCI specifications. Each of these  
clock inputs can drive up to a quarter of the chip, or they  
can be grouped together to drive multiple quadrants.  
The clock input is buffered prior to clocking the R-cells. If  
not used as a clock it will behave as a regular I/O.  
TDO, I/O  
Test Data Output  
Serial output for boundary scan testing. In flexible mode,  
TDO is active when the TMS pin is set LOW (refer to  
Table 1-5 on page 1-9). This pin functions as an I/O when  
the boundary scan state machine reaches the "logic  
reset" state. When Silicon Explorer II is being used, TDO  
will act as an output when the "checksum" command is  
run. It will return to user IO when "checksum" is  
complete.  
GND  
Ground  
TMS  
Test Mode Select  
LOW supply voltage.  
The TMS pin controls the use of the IEEE 1149.1  
Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible  
mode when the TMS pin is set LOW, the TCK, TDI, and  
TDO pins are boundary scan pins (refer to Table 1-5 on  
page 1-9). Once the boundary scan pins are in test mode,  
they will remain in that mode until the internal  
boundary scan state machine reaches the “logic reset”  
state. At this point, the boundary scan pins will be  
released and will function as regular I/O pins. The “logic  
reset” state is reached 5 TCK cycles after the TMS pin is  
set HIGH. In dedicated test mode, TMS functions as  
specified in the IEEE 1149.1 specifications.  
HCLK  
Dedicated (Hardwired)  
Array Clock  
This pin is the clock input for sequential modules. Input  
levels are compatible with LVTTL or 3.3 V PCI  
specifications. This input is directly wired to each R-cell  
and offers clock speeds independent of the number of R-  
cells being driven. If not used, this pin must be set LOW  
or HIGH on the board and must not be left floating.  
I/O  
Input/Output  
The I/O pin functions as an input, output, tristate or  
bidirectional buffer. Based on certain configurations,  
input and output levels are compatible with LVTTL or  
3.3 V PCI specifications. Unused I/O pins are  
automatically tristated by the Designer software.  
TRST, I/O  
Boundary Scan Reset Pin  
Once it is configured as the JTAG Reset pin, the TRST pin  
functions as an active-low input to asynchronously  
initialize or reset the boundary scan circuit. The TRST pin  
is equipped with an internal pull-up resistor. This pin  
functions as an I/O when the “Reserve JTAG Reset Pin” is  
not selected in Designer.  
NC  
No Connection  
This pin is not connected to circuitry within the device.  
These pins can be driven to any voltage or can be left  
floating with no effect on the operation of the device.  
V
Supply Voltage  
CCI  
Supply voltage for I/Os. See “Recommended Operating  
Conditions” on page 1-13. All VCCI power pins in the  
device should be connected.  
PRA, I/O  
Probe A/B  
PRB, I/O  
The Probe pin is used to output data from any user-  
defined design node within the device. This independent  
diagnostic pin can be used in conjunction with the other  
probe pin to allow real-time diagnostic output of any  
signal path within the device. The Probe pin can be used  
as a user-defined I/O when verification has been  
completed. The pin’s probe capabilities can be  
permanently disabled to protect programmed design  
confidentiality.  
V
Supply Voltage  
CCA  
Supply voltage for Array. See “Recommended Operating  
Conditions” on page 1-13. All VCCA power pins in the  
device should be connected.  
1-38  
v2.2  
Package Pin Assignments  
208-Pin PQFP (Top View)  
208  
1
208-Pin PQFP  
Figure 2-1 208-Pin PQFP  
Note  
For Package Manufacturing and Environmental information, visit Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
v2.2  
2-1  
208-Pin PQFP  
208-Pin PQFP  
Pin  
A54SX08A A54SX16A A54SX32A A54SX72A  
Pin  
A54SX08A A54SX16A A54SX32A A54SX72A  
Number  
Function  
GND  
TDI, I/O  
I/O  
Function  
GND  
TDI, I/O  
I/O  
Function  
GND  
TDI, I/O  
I/O  
Function  
GND  
TDI, I/O  
I/O  
Number  
Function  
Function  
Function  
Function  
1
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
I/O  
I/O  
I/O  
I/O  
2
I/O  
I/O  
I/O  
I/O  
3
I/O  
I/O  
I/O  
I/O  
4
NC  
I/O  
I/O  
I/O  
NC  
VCCI  
VCCA  
I/O  
I/O  
I/O  
I/O  
5
I/O  
I/O  
I/O  
I/O  
VCCI  
VCCA  
I/O  
VCCI  
VCCA  
I/O  
VCCI  
VCCA  
I/O  
6
NC  
I/O  
I/O  
I/O  
7
I/O  
I/O  
I/O  
I/O  
8
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
9
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TMS  
VCCI  
I/O  
TMS  
VCCI  
I/O  
TMS  
VCCI  
I/O  
TMS  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
GND  
I/O  
GND  
I/O  
GND  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
GND  
VCCA  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
NC  
NC  
I/O  
VCCI  
NC  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
GND  
VCCA  
GND  
I/O  
GND  
VCCA  
GND  
I/O  
GND  
VCCA  
GND  
I/O  
GND  
VCCA  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
TRST, I/O  
NC  
TRST, I/O  
I/O  
TRST, I/O  
I/O  
TRST, I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
2-2  
v2.2  
208-Pin PQFP  
208-Pin PQFP  
Pin  
A54SX08A A54SX16A A54SX32A A54SX72A  
Pin  
A54SX08A A54SX16A A54SX32A A54SX72A  
Number  
Function  
Function  
Function  
Function  
Number  
Function  
NC  
I/O  
Function  
Function  
Function  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
103  
104  
105  
I/O  
I/O  
I/O  
I/O  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
QCLKA, I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
PRB, I/O  
GND  
VCCA  
GND  
NC  
PRB, I/O  
GND  
VCCA  
GND  
NC  
PRB, I/O  
GND  
VCCA  
GND  
NC  
PRB,I/O  
GND  
VCCA  
GND  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
VCCI  
NC  
I/O  
VCCA  
VCCI  
I/O  
VCCA  
VCCI  
I/O  
VCCA  
VCCI  
GND  
VCCA  
I/O  
I/O  
I/O  
I/O  
I/O  
HCLK  
I/O  
HCLK  
I/O  
HCLK  
I/O  
HCLK  
VCCI  
QCLKB, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
GND  
VCCA  
GND  
NC  
I/O  
GND  
VCCA  
GND  
NC  
I/O  
GND  
VCCA  
GND  
NC  
I/O  
GND  
VCCA  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
GND  
GND  
GND  
I/O  
I/O  
I/O  
I/O  
v2.2  
2-3  
208-Pin PQFP  
208-Pin PQFP  
Pin  
A54SX08A A54SX16A A54SX32A A54SX72A  
Pin  
A54SX08A A54SX16A A54SX32A A54SX72A  
Number  
Function  
NC  
I/O  
Function  
Function  
Function  
Number  
Function  
Function  
Function  
Function  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
I/O  
I/O  
I/O  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
QCLKD, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
GND  
I/O  
VCCA  
GND  
I/O  
VCCA  
GND  
I/O  
VCCA  
GND  
I/O  
CLKA  
CLKB  
NC  
CLKA  
CLKB  
NC  
CLKA  
CLKB  
NC  
CLKA, I/O  
CLKB, I/O  
NC  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
GND  
VCCA  
GND  
PRA, I/O  
I/O  
GND  
VCCA  
GND  
PRA, I/O  
I/O  
GND  
VCCA  
GND  
PRA, I/O  
I/O  
GND  
VCCA  
GND  
PRA, I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
NC  
NC  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
QCLKC, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
GND  
I/O  
GND  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
NC  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
TCK, I/O  
TCK, I/O  
TCK, I/O  
TCK, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
2-4  
v2.2  
100-Pin TQFP (Top View)  
100  
1
100-Pin  
TQFP  
Figure 2-2 100-Pin TQFP  
Note  
For Package Manufacturing and Environmental information, visit Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
v2.2  
2-5  
100-TQFP  
100-TQFP  
A54SX08A  
A54SX16A  
Function  
A54SX32A  
Function  
A54SX08A  
A54SX16A  
Function  
A54SX32A  
Function  
Pin Number  
Pin Number  
Function  
GND  
TDI, I/O  
I/O  
Function  
GND  
NC  
1
GND  
TDI, I/O  
I/O  
GND  
TDI, I/O  
I/O  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
GND  
NC  
GND  
NC  
2
3
I/O  
I/O  
I/O  
4
I/O  
I/O  
I/O  
HCLK  
I/O  
HCLK  
I/O  
HCLK  
I/O  
5
I/O  
I/O  
I/O  
6
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
7
TMS  
VCCI  
GND  
I/O  
TMS  
VCCI  
GND  
I/O  
TMS  
VCCI  
GND  
I/O  
I/O  
I/O  
I/O  
8
I/O  
I/O  
I/O  
9
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
I/O  
I/O  
I/O  
TRST, I/O  
I/O  
TRST, I/O  
I/O  
TRST, I/O  
I/O  
GND  
I/O  
GND  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
VCCI  
I/O  
VCCA  
VCCI  
I/O  
VCCA  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
GND  
GND  
I/O  
VCCA  
GND  
GND  
I/O  
VCCA  
GND  
GND  
I/O  
I/O  
I/O  
I/O  
PRB, I/O  
VCCA  
PRB, I/O  
VCCA  
PRB, I/O  
VCCA  
2-6  
v2.2  
100-TQFP  
A54SX08A  
Function  
A54SX16A  
Function  
A54SX32A  
Function  
Pin Number  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CLKA  
CLKB  
NC  
CLKA  
CLKB  
NC  
CLKA  
CLKB  
NC  
VCCA  
GND  
PRA, I/O  
I/O  
VCCA  
GND  
PRA, I/O  
I/O  
VCCA  
GND  
PRA, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TCK, I/O  
TCK, I/O  
TCK, I/O  
v2.2  
2-7  
144-Pin TQFP (Top View)  
144  
1
144-Pin  
TQFP  
Figure 2-3 144-Pin TQFP  
Note  
For Package Manufacturing and Environmental information, visit Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
2-8  
v2.2  
144-Pin TQFP  
144-Pin TQFP  
A54SX08A  
A54SX16A  
Function  
A54SX32A  
Function  
A54SX08A  
Function  
A54SX16A  
Function  
A54SX32A  
Function  
Pin Number  
Pin Number  
Function  
GND  
TDI, I/O  
I/O  
1
GND  
TDI, I/O  
I/O  
GND  
TDI, I/O  
I/O  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
I/O  
I/O  
I/O  
I/O  
I/O  
2
I/O  
3
I/O  
I/O  
I/O  
4
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
5
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
6
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
7
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
8
I/O  
I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
9
TMS  
VCCI  
GND  
I/O  
TMS  
VCCI  
GND  
I/O  
TMS  
VCCI  
GND  
I/O  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
PRB, I/O  
I/O  
PRB, I/O  
I/O  
PRB, I/O  
I/O  
NC  
NC  
NC  
VCCA  
I/O  
VCCA  
I/O  
VCCA  
I/O  
VCCA  
GND  
NC  
VCCA  
GND  
NC  
VCCA  
GND  
NC  
TRST, I/O  
I/O  
TRST, I/O  
I/O  
TRST, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
HCLK  
I/O  
HCLK  
I/O  
HCLK  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
VCCI  
VCCA  
I/O  
GND  
VCCI  
VCCA  
I/O  
GND  
VCCI  
VCCA  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
GND  
GND  
GND  
v2.2  
2-9  
144-Pin TQFP  
144-Pin TQFP  
A54SX08A  
A54SX16A  
Function  
A54SX32A  
Function  
A54SX08A  
A54SX16A  
Function  
A54SX32A  
Function  
Pin Number  
Pin Number  
Function  
GND  
I/O  
Function  
GND  
I/O  
73  
74  
GND  
I/O  
GND  
I/O  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
GND  
I/O  
GND  
I/O  
75  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
76  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
77  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
78  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
79  
VCCA  
VCCI  
GND  
I/O  
VCCA  
VCCI  
GND  
I/O  
VCCA  
VCCI  
GND  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
80  
81  
I/O  
I/O  
I/O  
82  
I/O  
I/O  
I/O  
83  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
84  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
85  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
86  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
87  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
88  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
89  
VCCA  
NC  
VCCA  
NC  
I/O  
VCCA  
NC  
I/O  
CLKA  
CLKB  
NC  
CLKA  
CLKB  
NC  
CLKA  
CLKB  
NC  
90  
91  
I/O  
92  
I/O  
I/O  
I/O  
GND  
VCCA  
I/O  
GND  
VCCA  
I/O  
GND  
VCCA  
I/O  
93  
I/O  
I/O  
I/O  
94  
I/O  
I/O  
I/O  
95  
I/O  
I/O  
I/O  
PRA, I/O  
I/O  
PRA, I/O  
I/O  
PRA, I/O  
I/O  
96  
I/O  
I/O  
I/O  
97  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
98  
VCCA  
GND  
I/O  
VCCA  
GND  
I/O  
VCCA  
GND  
I/O  
I/O  
I/O  
I/O  
99  
I/O  
I/O  
I/O  
100  
101  
102  
103  
104  
105  
106  
107  
108  
I/O  
I/O  
I/O  
GND  
VCCI  
I/O  
GND  
VCCI  
I/O  
GND  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TCK, I/O  
TCK, I/O  
TCK, I/O  
2-10  
v2.2  
144-Pin FBGA (Top View)  
4
1
2
3
5
6
7
8
10 11 12  
9
A
B
C
D
E
F
G
H
J
K
L
M
Figure 2-4 144-Pin FBGA  
Note  
For Package Manufacturing and Environmental information, visit Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
v2.2  
2-11  
144-Pin FGBA  
144-Pin FGBA  
A54SX08A  
Function  
A54SX16A  
Function  
A54SX32A  
Function  
A54SX08A  
Function  
A54SX16A  
Function  
A54SX32A  
Function  
Pin Number  
Pin Number  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
A12  
B1  
I/O  
I/O  
I/O  
I/O  
I/O  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
D10  
D11  
D12  
E1  
I/O  
I/O  
VCCI  
TDI, I/O  
I/O  
I/O  
VCCI  
TDI, I/O  
I/O  
I/O  
VCCI  
TDI, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
GND  
CLKA  
I/O  
VCCA  
GND  
CLKA  
I/O  
VCCA  
GND  
CLKA  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
B2  
GND  
I/O  
GND  
I/O  
GND  
I/O  
E2  
I/O  
I/O  
I/O  
B3  
E3  
I/O  
I/O  
I/O  
B4  
I/O  
I/O  
I/O  
E4  
I/O  
I/O  
I/O  
B5  
I/O  
I/O  
I/O  
E5  
TMS  
VCCI  
VCCI  
VCCI  
VCCA  
I/O  
TMS  
VCCI  
VCCI  
VCCI  
VCCA  
I/O  
TMS  
VCCI  
VCCI  
VCCI  
VCCA  
I/O  
B6  
I/O  
I/O  
I/O  
E6  
B7  
CLKB  
I/O  
CLKB  
I/O  
CLKB  
I/O  
E7  
B8  
E8  
B9  
I/O  
I/O  
I/O  
E9  
B10  
B11  
B12  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
C10  
C11  
C12  
I/O  
I/O  
I/O  
E10  
E11  
E12  
F1  
GND  
I/O  
GND  
I/O  
GND  
I/O  
GND  
I/O  
GND  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
F2  
I/O  
I/O  
I/O  
TCK, I/O  
I/O  
TCK, I/O  
I/O  
TCK, I/O  
I/O  
F3  
NC  
NC  
NC  
F4  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
F5  
GND  
GND  
GND  
VCCI  
I/O  
GND  
GND  
GND  
VCCI  
I/O  
GND  
GND  
GND  
VCCI  
I/O  
PRA, I/O  
I/O  
PRA, I/O  
I/O  
PRA, I/O  
I/O  
F6  
F7  
I/O  
I/O  
I/O  
F8  
I/O  
I/O  
I/O  
F9  
I/O  
I/O  
I/O  
F10  
F11  
F12  
GND  
I/O  
GND  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
2-12  
v2.2  
144-Pin FGBA  
144-Pin FGBA  
A54SX08A  
Function  
A54SX16A  
Function  
A54SX32A  
Function  
A54SX08A  
Function  
A54SX16A  
Function  
A54SX32A  
Function  
Pin Number  
Pin Number  
G1  
G2  
G3  
G4  
G5  
G6  
G7  
G8  
G9  
G10  
G11  
G12  
H1  
H2  
H3  
H4  
H5  
H6  
H7  
H8  
H9  
H10  
H11  
H12  
J1  
I/O  
I/O  
GND  
I/O  
I/O  
GND  
I/O  
K1  
K2  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
K3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
K4  
I/O  
I/O  
I/O  
GND  
GND  
GND  
VCCI  
I/O  
GND  
GND  
GND  
VCCI  
I/O  
GND  
GND  
GND  
VCCI  
I/O  
K5  
I/O  
I/O  
I/O  
K6  
I/O  
I/O  
I/O  
K7  
GND  
I/O  
GND  
I/O  
GND  
I/O  
K8  
K9  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
K10  
K11  
K12  
L1  
GND  
I/O  
GND  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TRST, I/O  
I/O  
TRST, I/O  
I/O  
TRST, I/O  
I/O  
GND  
I/O  
GND  
I/O  
GND  
I/O  
L2  
I/O  
I/O  
I/O  
L3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
L4  
I/O  
I/O  
I/O  
VCCA  
VCCA  
VCCI  
VCCI  
VCCA  
I/O  
VCCA  
VCCA  
VCCI  
VCCI  
VCCA  
I/O  
VCCA  
VCCA  
VCCI  
VCCI  
VCCA  
I/O  
L5  
I/O  
I/O  
I/O  
L6  
I/O  
I/O  
I/O  
L7  
HCLK  
I/O  
HCLK  
I/O  
HCLK  
I/O  
L8  
L9  
I/O  
I/O  
I/O  
L10  
L11  
L12  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
M8  
M9  
M10  
M11  
M12  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
NC  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
J2  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
J3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
J4  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
J5  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
J6  
PRB, I/O  
I/O  
PRB, I/O  
I/O  
PRB, I/O  
I/O  
I/O  
I/O  
I/O  
J7  
VCCA  
I/O  
VCCA  
I/O  
VCCA  
I/O  
J8  
I/O  
I/O  
I/O  
J9  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
J10  
J11  
J12  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
VCCA  
VCCA  
VCCA  
v2.2  
2-13  
256-Pin FBGA (Top View)  
1
2
3
4
6
7
8
9 10 11 12  
13 14  
5
15 16  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Figure 2-5 256-Pin FBGA  
Note  
For Package Manufacturing and Environmental information, visit Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
2-14  
v2.2  
256-Pin FBGA  
256-Pin FBGA  
A54SX16A  
A54SX32A  
Function  
A54SX72A  
Function  
A54SX16A  
Function  
A54SX32A  
Function  
A54SX72A  
Function  
Pin Number  
Pin Number  
Function  
GND  
TCK, I/O  
I/O  
A1  
A2  
GND  
TCK, I/O  
I/O  
GND  
TCK, I/O  
I/O  
C4  
C5  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
A3  
C6  
I/O  
I/O  
A4  
I/O  
I/O  
I/O  
C7  
I/O  
I/O  
I/O  
A5  
I/O  
I/O  
I/O  
C8  
I/O  
I/O  
I/O  
A6  
I/O  
I/O  
I/O  
C9  
CLKA  
I/O  
CLKA  
I/O  
CLKA, I/O  
I/O  
A7  
I/O  
I/O  
I/O  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
D1  
A8  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
A9  
CLKB  
I/O  
CLKB  
I/O  
CLKB, I/O  
I/O  
I/O  
I/O  
I/O  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
B1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
GND  
I/O  
GND  
GND  
I/O  
GND  
GND  
I/O  
D2  
I/O  
I/O  
I/O  
D3  
I/O  
I/O  
I/O  
D4  
I/O  
I/O  
I/O  
B2  
GND  
I/O  
GND  
I/O  
GND  
I/O  
D5  
I/O  
I/O  
I/O  
B3  
D6  
I/O  
I/O  
I/O  
B4  
I/O  
I/O  
I/O  
D7  
I/O  
I/O  
I/O  
B5  
I/O  
I/O  
I/O  
D8  
PRA, I/O  
I/O  
PRA, I/O  
I/O  
PRA, I/O  
QCLKD, I/O  
I/O  
B6  
NC  
I/O  
I/O  
D9  
B7  
I/O  
I/O  
I/O  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
E1  
I/O  
I/O  
B8  
VCCA  
I/O  
VCCA  
I/O  
VCCA  
I/O  
NC  
I/O  
I/O  
I/O  
B9  
I/O  
I/O  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
C1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
GND  
I/O  
GND  
I/O  
E2  
I/O  
I/O  
I/O  
E3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
E4  
I/O  
I/O  
I/O  
C2  
TDI, I/O  
GND  
TDI, I/O  
GND  
TDI, I/O  
GND  
E5  
I/O  
I/O  
I/O  
C3  
E6  
I/O  
I/O  
I/O  
v2.2  
2-15  
256-Pin FBGA  
256-Pin FBGA  
A54SX16A  
Function  
A54SX32A  
Function  
A54SX72A  
Function  
A54SX16A  
A54SX32A  
Function  
A54SX72A  
Function  
Pin Number  
Pin Number  
Function  
GND  
VCCI  
I/O  
E7  
E8  
I/O  
I/O  
I/O  
QCLKC, I/O  
I/O  
G10  
G11  
G12  
G13  
G14  
G15  
G16  
H1  
GND  
VCCI  
I/O  
GND  
VCCI  
I/O  
I/O  
E9  
I/O  
I/O  
I/O  
E10  
E11  
E12  
E13  
E14  
E15  
E16  
F1  
I/O  
I/O  
I/O  
GND  
NC  
GND  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
I/O  
VCCA  
I/O  
VCCA  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
H2  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
H3  
VCCA  
TRST, I/O  
I/O  
VCCA  
TRST, I/O  
I/O  
VCCA  
TRST, I/O  
I/O  
I/O  
I/O  
I/O  
H4  
F2  
I/O  
I/O  
I/O  
H5  
F3  
I/O  
I/O  
I/O  
H6  
VCCI  
GND  
GND  
GND  
GND  
VCCI  
I/O  
VCCI  
GND  
GND  
GND  
GND  
VCCI  
I/O  
VCCI  
GND  
GND  
GND  
GND  
VCCI  
I/O  
F4  
TMS  
I/O  
TMS  
I/O  
TMS  
I/O  
H7  
F5  
H8  
I/O  
I/O  
I/O  
H9  
F6  
F7  
VCCI  
VCCI  
VCCI  
VCCI  
I/O  
VCCI  
VCCI  
VCCI  
VCCI  
I/O  
VCCI  
VCCI  
VCCI  
VCCI  
I/O  
H10  
H11  
H12  
H13  
H14  
H15  
H16  
J1  
F8  
F9  
F10  
F11  
F12  
F13  
F14  
F15  
F16  
G1  
G2  
G3  
G4  
G5  
G6  
G7  
G8  
G9  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
I/O  
VCCA  
I/O  
VCCA  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
J2  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
J3  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
J4  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
J5  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
J6  
VCCI  
GND  
GND  
GND  
GND  
VCCI  
I/O  
VCCI  
GND  
GND  
GND  
GND  
VCCI  
I/O  
VCCI  
GND  
GND  
GND  
GND  
VCCI  
I/O  
I/O  
I/O  
I/O  
J7  
I/O  
I/O  
I/O  
J8  
VCCI  
GND  
GND  
GND  
VCCI  
GND  
GND  
GND  
VCCI  
GND  
GND  
GND  
J9  
J10  
J11  
J12  
2-16  
v2.2  
256-Pin FBGA  
256-Pin FBGA  
A54SX16A  
Function  
A54SX32A  
Function  
A54SX72A  
Function  
A54SX16A  
A54SX32A  
Function  
A54SX72A  
Function  
Pin Number  
Pin Number  
Function  
NC  
I/O  
J13  
J14  
J15  
J16  
K1  
I/O  
I/O  
I/O  
I/O  
I/O  
L16  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
M8  
M9  
M10  
M11  
M12  
M13  
M14  
M15  
M16  
N1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
PRB, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
K2  
I/O  
I/O  
I/O  
I/O  
I/O  
K3  
NC  
I/O  
I/O  
I/O  
I/O  
K4  
VCCA  
I/O  
VCCA  
I/O  
VCCA  
I/O  
I/O  
QCLKA, I/O  
PRB, I/O  
I/O  
K5  
PRB, I/O  
I/O  
K6  
VCCI  
GND  
GND  
GND  
GND  
VCCI  
I/O  
VCCI  
GND  
GND  
GND  
GND  
VCCI  
I/O  
VCCI  
GND  
GND  
GND  
GND  
VCCI  
I/O  
K7  
I/O  
I/O  
K8  
I/O  
I/O  
K9  
NC  
I/O  
I/O  
K10  
K11  
K12  
K13  
K14  
K15  
K16  
L1  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
N2  
I/O  
I/O  
I/O  
I/O  
I/O  
N3  
I/O  
I/O  
I/O  
I/O  
I/O  
N4  
I/O  
I/O  
L2  
I/O  
I/O  
I/O  
N5  
I/O  
I/O  
L3  
I/O  
I/O  
I/O  
N6  
I/O  
I/O  
L4  
I/O  
I/O  
I/O  
N7  
I/O  
I/O  
L5  
I/O  
I/O  
I/O  
N8  
I/O  
I/O  
L6  
I/O  
I/O  
I/O  
N9  
I/O  
I/O  
L7  
VCCI  
VCCI  
VCCI  
VCCI  
I/O  
VCCI  
VCCI  
VCCI  
VCCI  
I/O  
VCCI  
VCCI  
VCCI  
VCCI  
I/O  
N10  
N11  
N12  
N13  
N14  
N15  
N16  
P1  
I/O  
I/O  
L8  
I/O  
I/O  
L9  
I/O  
I/O  
L10  
L11  
L12  
L13  
L14  
L15  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
P2  
GND  
GND  
v2.2  
2-17  
256-Pin FBGA  
256-Pin FBGA  
A54SX16A  
Function  
A54SX32A  
Function  
A54SX72A  
Function  
A54SX16A  
Function  
A54SX32A  
Function  
A54SX72A  
Function  
Pin Number  
Pin Number  
P3  
P4  
I/O  
I/O  
I/O  
I/O  
I/O  
T6  
T7  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
P5  
NC  
I/O  
I/O  
T8  
I/O  
I/O  
I/O  
P6  
I/O  
I/O  
I/O  
T9  
VCCA  
I/O  
VCCA  
I/O  
VCCA  
I/O  
P7  
I/O  
I/O  
I/O  
T10  
T11  
T12  
T13  
T14  
T15  
T16  
P8  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
P9  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
P10  
P11  
P12  
P13  
P14  
P15  
P16  
R1  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TDO, I/O  
GND  
TDO, I/O  
GND  
TDO, I/O  
GND  
VCCA  
I/O  
VCCA  
I/O  
VCCA  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
R2  
GND  
I/O  
GND  
I/O  
GND  
I/O  
R3  
R4  
NC  
I/O  
I/O  
R5  
I/O  
I/O  
I/O  
R6  
I/O  
I/O  
I/O  
R7  
I/O  
I/O  
I/O  
R8  
I/O  
I/O  
I/O  
R9  
HCLK  
I/O  
HCLK  
I/O  
HCLK  
QCLKB, I/O  
I/O  
R10  
R11  
R12  
R13  
R14  
R15  
R16  
T1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
GND  
GND  
I/O  
GND  
GND  
GND  
I/O  
GND  
GND  
GND  
I/O  
T2  
T3  
I/O  
I/O  
I/O  
T4  
NC  
I/O  
I/O  
T5  
I/O  
I/O  
I/O  
2-18  
v2.2  
Package Pin Assignments  
484-Pin FBGA (Top View)  
1
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26  
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA  
AB  
AC  
AD  
AE  
AF  
Figure 2-6 484-Pin FBGA  
Note  
For Package Manufacturing and Environmental information, visit Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
v2.2  
19  
484-Pin FBGA  
484-Pin FBGA  
484-Pin FBGA  
A54SX72A  
A54SX72A  
Function  
A54SX72A  
Function  
Pin Number  
Pin Number  
Pin Number  
Function  
NC  
NC  
I/O  
A1  
A2  
AA26  
AB1  
I/O  
AC9  
AC10  
AC11  
AC12  
AC13  
AC14  
AC15  
AC16  
AC17  
AC18  
AC19  
AC20  
AC21  
AC22  
AC23  
AC24  
AC25  
AC26  
AD1  
I/O  
NC  
I/O  
A3  
AB2  
VCCI  
I/O  
I/O  
A4  
I/O  
AB3  
QCLKA, I/O  
I/O  
A5  
I/O  
AB4  
I/O  
A6  
I/O  
AB5  
I/O  
I/O  
A7  
I/O  
AB6  
I/O  
I/O  
A8  
I/O  
AB7  
I/O  
I/O  
A9  
I/O  
AB8  
I/O  
I/O  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
AA1  
AA2  
AA3  
AA4  
AA5  
AA22  
AA23  
AA24  
AA25  
I/O  
AB9  
I/O  
I/O  
I/O  
AB10  
AB11  
AB12  
AB13  
AB14  
AB15  
AB16  
AB17  
AB18  
AB19  
AB20  
AB21  
AB22  
AB23  
AB24  
AB25  
AB26  
AC1  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
I/O  
PRB, I/O  
VCCA  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
AD2  
I/O  
I/O  
TDO, I/O  
GND  
I/O  
AD3  
GND  
I/O  
I/O  
AD4  
I/O  
AD5  
I/O  
I/O  
I/O  
AD6  
I/O  
NC  
NC  
I/O  
I/O  
AD7  
I/O  
I/O  
AD8  
I/O  
I/O  
AD9  
VCCI  
I/O  
I/O  
I/O  
AD10  
AD11  
AD12  
AD13  
AD14  
AD15  
AD16  
AD17  
VCCA  
I/O  
AC2  
I/O  
I/O  
AC3  
I/O  
I/O  
I/O  
AC4  
I/O  
VCCI  
I/O  
I/O  
AC5  
VCCI  
I/O  
I/O  
AC6  
I/O  
I/O  
AC7  
VCCI  
I/O  
I/O  
I/O  
AC8  
VCCI  
20  
v2.2  
Package Pin Assignments  
484-Pin FBGA  
484-Pin FBGA  
484-Pin FBGA  
A54SX72A  
A54SX72A  
A54SX72A  
Pin Number  
Pin Number  
Pin Number  
Function  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
NC  
Function  
Function  
AD18  
AD19  
AD20  
AD21  
AD22  
AD23  
AD24  
AD25  
AD26  
AE1  
AF1  
AF2  
AF3  
AF4  
AF5  
AF6  
AF7  
AF8  
AF9  
AF10  
AF11  
AF12  
AF13  
AF14  
AF15  
AF16  
AF17  
AF18  
AF19  
AF20  
AF21  
AF22  
AF23  
AF24  
AF25  
AF26  
B1  
NC  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
C1  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
VCCI  
CLKA, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
I/O  
AE2  
I/O  
I/O  
AE3  
NC  
I/O  
AE4  
HCLK  
QCLKB, I/O  
I/O  
I/O  
AE5  
I/O  
AE6  
I/O  
AE7  
I/O  
I/O  
AE8  
I/O  
NC  
AE9  
I/O  
I/O  
AE10  
AE11  
AE12  
AE13  
AE14  
AE15  
AE16  
AE17  
AE18  
AE19  
AE20  
AE21  
AE22  
AE23  
AE24  
AE25  
AE26  
I/O  
C2  
I/O  
I/O  
C3  
I/O  
I/O  
C4  
I/O  
I/O  
C5  
I/O  
I/O  
C6  
VCCI  
I/O  
I/O  
C7  
NC  
C8  
I/O  
NC  
C9  
VCCI  
I/O  
NC  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
B2  
NC  
I/O  
B3  
I/O  
I/O  
B4  
I/O  
PRA, I/O  
I/O  
B5  
I/O  
B6  
I/O  
QCLKD, I/O  
I/O  
B7  
I/O  
B8  
I/O  
I/O  
B9  
I/O  
I/O  
v2.2  
21  
484-Pin FBGA  
484-Pin FBGA  
484-Pin FBGA  
A54SX72A  
Function  
A54SX72A  
Function  
A54SX72A  
Function  
Pin Number  
Pin Number  
Pin Number  
C19  
C20  
C21  
C22  
C23  
C24  
C25  
C26  
D1  
I/O  
E2  
E3  
I/O  
G1  
G2  
G3  
G4  
G5  
G22  
G23  
G24  
G25  
G26  
H1  
I/O  
VCCI  
I/O  
I/O  
I/O  
E4  
I/O  
I/O  
I/O  
E5  
GND  
TDI, IO  
I/O  
I/O  
I/O  
E6  
I/O  
I/O  
E7  
I/O  
I/O  
E8  
I/O  
VCCA  
I/O  
I/O  
E9  
I/O  
I/O  
E10  
E11  
E12  
E13  
E14  
E15  
E16  
E17  
E18  
E19  
E20  
E21  
E22  
E23  
E24  
E25  
E26  
F1  
I/O  
I/O  
D2  
TMS  
I/O  
I/O  
I/O  
D3  
I/O  
I/O  
D4  
VCCI  
I/O  
VCCA  
CLKB, I/O  
I/O  
H2  
I/O  
D5  
H3  
I/O  
D6  
TCK, I/O  
I/O  
H4  
I/O  
D7  
I/O  
H5  
I/O  
D8  
I/O  
I/O  
H22  
H23  
H24  
H25  
H26  
J1  
I/O  
D9  
I/O  
I/O  
I/O  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
D21  
D22  
D23  
D24  
D25  
D26  
E1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
QCLKC, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
J2  
I/O  
I/O  
I/O  
J3  
I/O  
I/O  
VCCI  
GND  
VCCI  
I/O  
J4  
I/O  
I/O  
J5  
I/O  
I/O  
J22  
J23  
J24  
J25  
J26  
K1  
I/O  
I/O  
F2  
I/O  
I/O  
F3  
I/O  
I/O  
VCCI  
GND  
I/O  
F4  
I/O  
VCCI  
I/O  
F5  
I/O  
F22  
F23  
F24  
F25  
F26  
I/O  
I/O  
I/O  
I/O  
K2  
VCCI  
I/O  
I/O  
I/O  
K3  
I/O  
I/O  
K4  
I/O  
I/O  
I/O  
K5  
VCCA  
22  
v2.2  
Package Pin Assignments  
484-Pin FBGA  
484-Pin FBGA  
484-Pin FBGA  
A54SX72A  
A54SX72A  
A54SX72A  
Pin Number  
Pin Number  
Pin Number  
Function  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
I/O  
Function  
Function  
K10  
K11  
K12  
K13  
K14  
K15  
K16  
K17  
K22  
K23  
K24  
K25  
K26  
L1  
M5  
M10  
M11  
M12  
M13  
M14  
M15  
M16  
M17  
M22  
M23  
M24  
M25  
M26  
N1  
I/O  
P4  
I/O  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
I/O  
P5  
VCCA  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
I/O  
P10  
P11  
P12  
P13  
P14  
P15  
P16  
P17  
P22  
P23  
P24  
P25  
P26  
R1  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
I/O  
I/O  
L2  
I/O  
I/O  
I/O  
L3  
I/O  
N2  
VCCI  
I/O  
I/O  
L4  
I/O  
N3  
R2  
I/O  
L5  
I/O  
N4  
I/O  
R3  
I/O  
L10  
L11  
L12  
L13  
L14  
L15  
L16  
L17  
L22  
L23  
L24  
L25  
L26  
M1  
M2  
M3  
M4  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
I/O  
N5  
I/O  
R4  
I/O  
N10  
N11  
N12  
N13  
N14  
N15  
N16  
N17  
N22  
N23  
N24  
N25  
N26  
P1  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VCCA  
I/O  
R5  
TRST, I/O  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
I/O  
R10  
R11  
R12  
R13  
R14  
R15  
R16  
R17  
R22  
R23  
R24  
R25  
R26  
T1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
P2  
I/O  
I/O  
I/O  
P3  
I/O  
T2  
I/O  
v2.2  
23  
484-Pin FBGA  
484-Pin FBGA  
A54SX72A  
Function  
A54SX72A  
Function  
Pin Number  
Pin Number  
T3  
I/O  
V2  
V3  
I/O  
T4  
I/O  
I/O  
T5  
I/O  
V4  
I/O  
T10  
T11  
T12  
T13  
T14  
T15  
T16  
T17  
T22  
T23  
T24  
T25  
T26  
U1  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
I/O  
V5  
I/O  
V22  
V23  
V24  
V25  
V26  
W1  
W2  
W3  
W4  
W5  
W22  
W23  
W24  
W25  
W26  
Y1  
VCCA  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
I/O  
I/O  
U2  
VCCI  
I/O  
I/O  
U3  
I/O  
U4  
I/O  
I/O  
U5  
I/O  
Y2  
I/O  
U10  
U11  
U12  
U13  
U14  
U15  
U16  
U17  
U22  
U23  
U24  
U25  
U26  
V1  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
I/O  
Y3  
I/O  
Y4  
I/O  
Y5  
I/O  
Y22  
Y23  
Y24  
Y25  
Y26  
I/O  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
I/O  
24  
v2.2  
Datasheet Information  
List of Changes  
The following table lists critical changes that were made in the current version of the document.  
Previous version Changes in current version (v2.2)  
Page  
ii  
v2.1  
RoHS information was added to the "Ordering Information".  
The Product Plan was removed because all of the devices have been fully characterized.  
The "Dedicated Mode" section was updated.  
May 2006  
N/A  
1-8  
The "Development Tool Support" section was updated.  
The "Programming" section was updated.  
Note 2 was added to Table 1-7 • Absolute Maximum Ratings1.  
1-11  
1-11  
1-13  
ii  
v2.0  
A note was added to the "Ordering Information".  
September 2003  
Note 1 was added to Table 1-8 • Recommended Operating Conditions.  
1-13  
Datasheet Categories  
In order to provide the latest information to designers, some datasheets are published before data has been fully  
characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Datasheet  
Supplement.” The definition of these categories are as follows:  
Product Brief  
The product brief is a summarized version of a datasheet (advanced or production) containing general product  
information. This brief gives an overview of specific device and family information.  
Advanced  
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed  
grades. This information can be used as estimates, but not for production.  
Unmarked (production)  
This datasheet version contains information that is considered to be final.  
Datasheet Supplement  
The datasheet supplement gives specific device information for a derivative family that differs from the general family  
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and  
for specifications that do not differ between the two families.  
Export Administration Regulations (EAR)  
The product described in this datasheet is subject to the Export Administration Regulations (EAR). They could require  
an approved export license prior to export from the United States. An export includes release of product or disclosure  
of technology to a foreign national inside or outside the United States.  
v2.2  
1
Actel and the Actel logo are registered trademarks of Actel Corporation.  
All other trademarks are the property of their owners.  
http://www.actel.com  
Actel Corporation  
Actel Europe Ltd.  
Actel Japan  
www.jp.actel.com  
Actel Hong Kong  
www.actel.com.cn  
2061 Stierlin Court  
Mountain View, CA  
94043-4655 USA  
Dunlop House, Riverside Way  
Camberley, Surrey GU15 3YL  
United Kingdom  
EXOS Ebisu Bldg. 4F  
1-24-14 Ebisu Shibuya-ku  
Tokyo 150 Japan  
Suite 2114, Two Pacific Place  
88 Queensway, Admiralty  
Hong Kong  
Phone 650.318.4200  
Fax 650.318.4600  
Phone +44 (0) 1276 401 450  
Fax +44 (0) 1276 401 490  
Phone +81.03.3445.7671  
Fax +81.03.3445.7668  
Phone +852 2185 6460  
Fax +852 2185 6488  
51700026-2/6.06  
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