General Description
Actel's SX-A family of FPGAs features a sea-of-modules
architecture. SX-A devices simplify design time, enable
dramatic reductions in design costs and power
consumption, and further decrease time-to-market for
SX-A Family Architecture
Programmable Interconnect Element
performance-intensive
applications.
With
the
The SX-A family provides efficient use of silicon by
locating the routing interconnect resources between the
top two metal layers (Figure 1-1). This completely
eliminates the channels of routing and interconnect
resources between logic modules (as implemented on
SRAM FPGAs and previous generations of antifuse
FPGAs), and enables the entire floor of the device to be
spanned with an uninterrupted grid of logic modules.
automotive temperature grade support (-40°C to 125°C),
the SX-A devices can address many in-cabin telematics
and automobile interconnect applications.
Actel’s SX-A architecture features two types of logic
modules, the combinatorial cell (C-cell) and the register
cell (R-cell), each optimized for fast and efficient
mapping of synthesized logic functions. The routing and
interconnect resources are in the metal layers above the
logic modules, providing optimal use of silicon. This
enables the entire floor of the device to be spanned with
an uninterrupted grid of fine-grained, synthesis-friendly
logic modules (or “sea-of-modules”), which reduces the
distance signals have to travel between logic modules. To
minimize signal propagation delay, SX-A devices employ
both local and general routing resources. The high-speed
local routing resources (DirectConnect and FastConnect)
enable very fast local signal propagation that is optimal
for fast counters, state machines, and datapath logic.
The general system of segmented routing tracks allows
any logic module in the array to be connected to any
other logic or I/O module. Within this system,
propagation delay is minimized by limiting the number
of antifuse interconnect elements to five (90 percent of
connections typically use only three or fewer antifuses).
The unique local and general routing structure featured
in SX-A devices gives fast and predictable performance,
allows 100% pin-locking with full logic utilization,
enables concurrent PCB development, reduces design
time, and allows designers to achieve performance goals
with minimum effort.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
antifuse interconnect elements. The antifuses are
normally open circuit and, when programmed, form a
permanent low-impedance connection.
The extremely small size of these interconnect elements
gives the automotive-grade SX-A devices abundant
routing resources and provides excellent protection
against design pirating. Reverse engineering is virtually
impossible because it is extremely difficult to distinguish
between programmed and unprogrammed antifuses,
and since SX-A is a nonvolatile, single-chip solution,
there is no configuration bitstream to intercept.
Additionally, the interconnect (i.e., the antifuses and
metal tracks) have lower capacitance and lower
resistance than any other device of similar capacity,
leading to the fastest signal propagation in the industry.
Logic Module Design
The SX-A family architecture is described as a “sea-of-
modules” architecture because the entire floor of the
device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. Actel’s SX-A family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
Further complementing SX-A’s flexible routing structure
is a hardwired, constantly loaded clock network that has
been tuned to provide fast clock propagation with
minimal clock skew. Additionally, the high performance
of the internal logic has eliminated the need to embed
latches or flip-flops in the I/O cells to achieve fast clock-
to-out or fast input set-up times. SX-A devices have easy-
to-use I/O cells that do not require HDL instantiation,
facilitating design re-use and reducing design and
verification time.
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure 1-2 on page 1-3).
The R-cell registers feature programmable clock polarity
selectable on a register-by-register basis. This provides
additional flexibility while allowing mapping of
synthesized functions into the SX-A FPGA. The clock
source for the R-cell can be chosen from either the
hardwired clock, the routed clocks, or internal logic.
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ACTEL [ Actel Corporation ]
