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A54SX16-P-1PQG208PP 参数 Datasheet PDF下载

A54SX16-P-1PQG208PP图片预览
型号: A54SX16-P-1PQG208PP
PDF下载: 下载PDF文件 查看货源
内容描述: SX系列FPGA [SX Family FPGAs]
分类和应用:
文件页数/大小: 64 页 / 504 K
品牌: ACTEL [ Actel Corporation ]
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SX Family FPGAs  
SX Family FPGAs  
General Description  
SX Family Architecture  
The SX family architecture was designed to satisfy next-  
generation performance and integration requirements  
for production-volume designs in a broad range of  
applications.  
The Actel SX family of FPGAs features a sea-of-modules  
architecture that delivers device performance and  
integration levels not currently achieved by any other  
FPGA architecture. SX devices greatly simplify design  
time, enable dramatic reductions in design costs and  
power consumption, and further decrease time to  
market for performance-intensive applications.  
Programmable Interconnect Element  
The SX family provides efficient use of silicon by locating  
the routing interconnect resources between the Metal 2  
(M2) and Metal 3 (M3) layers (Figure 1-1 on page 1-2).  
This completely eliminates the channels of routing and  
interconnect resources between logic modules (as  
implemented on SRAM FPGAs and previous generations  
of antifuse FPGAs), and enables the entire floor of the  
device to be spanned with an uninterrupted grid of logic  
modules.  
The Actel SX architecture features two types of logic  
modules, the combinatorial cell (C-cell) and the register  
cell (R-cell), each optimized for fast and efficient  
mapping of synthesized logic functions. The routing and  
interconnect resources are in the metal layers above the  
logic modules, providing optimal use of silicon. This  
enables the entire floor of the device to be spanned with  
an uninterrupted grid of fine-grained, synthesis-friendly  
logic modules (or “sea-of-modules”), which reduces the  
distance signals have to travel between logic modules. To  
minimize signal propagation delay, SX devices employ  
both local and general routing resources. The high-speed  
local routing resources (DirectConnect and FastConnect)  
enable very fast local signal propagation that is optimal  
for fast counters, state machines, and datapath logic.  
The general system of segmented routing tracks allows  
any logic module in the array to be connected to any  
other logic or I/O module. Within this system,  
propagation delay is minimized by limiting the number  
of antifuse interconnect elements to five (90 percent of  
connections typically use only three antifuses). The  
unique local and general routing structure featured in  
SX devices gives fast and predictable performance,  
allows 100 percent pin-locking with full logic utilization,  
enables concurrent PCB development, reduces design  
time, and allows designers to achieve performance goals  
with minimum effort.  
Interconnection between these logic modules is achieved  
using The Actel patented metal-to-metal programmable  
antifuse interconnect elements, which are embedded  
between the M2 and M3 layers. The antifuses are  
normally open circuit and, when programmed, form a  
permanent low-impedance connection.  
The extremely small size of these interconnect elements  
gives the SX family abundant routing resources and  
provides excellent protection against design pirating.  
Reverse engineering is virtually impossible because it is  
extremely difficult to distinguish between programmed  
and unprogrammed antifuses, and there is no  
configuration bitstream to intercept.  
Additionally, the interconnect elements (i.e., the  
antifuses and metal tracks) have lower capacitance and  
lower resistance than any other device of similar  
capacity, leading to the fastest signal propagation in the  
industry.  
Further complementing SX’s flexible routing structure is  
a hardwired, constantly loaded clock network that has  
been tuned to provide fast clock propagation with  
minimal clock skew. Additionally, the high performance  
of the internal logic has eliminated the need to embed  
latches or flip-flops in the I/O cells to achieve fast clock-  
to-out or fast input setup times. SX devices have easy to  
use I/O cells that do not require HDL instantiation,  
facilitating design reuse and reducing design and  
verification time.  
Logic Module Design  
The SX family architecture is described as a “sea-of-  
modules” architecture because the entire floor of the  
device is covered with a grid of logic modules with  
virtually no chip area lost to interconnect elements or  
routing. The Actel SX family provides two types of logic  
modules, the register cell (R-cell) and the combinatorial  
cell (C-cell).  
v3.2  
1-1  
SX Family FPGAs  
The R-cell contains a flip-flop featuring asynchronous  
clear, asynchronous preset, and clock enable (using the  
S0 and S1 lines) control signals (Figure 1-2). The R-cell  
registers feature programmable clock polarity selectable  
on a register-by-register basis. This provides additional  
flexibility while allowing mapping of synthesized  
functions into the SX FPGA. The clock source for the  
R-cell can be chosen from either the hardwired clock or  
the routed clock.  
Routing Tracks  
Metal 3  
Amorphous Silicon/  
Dielectric Antifuse  
Tungsten Plug Via  
Tungsten Plug Via  
Metal 2  
Metal 1  
Tungsten Plug  
Contact  
Silicon Substrate  
Figure 1-1 SX Family Interconnect Elements  
Routed Data Input  
S1  
S0  
PSETB  
Direct  
Connect  
Input  
D
Q
Y
HCLK  
CLKA, CLKB,  
Internal Logic  
CLRB  
CKS  
CKP  
Figure 1-2 R-Cell  
The C-cell implements a range of combinatorial functions  
up to 5-inputs (Figure 1-3 on page 1-3). Inclusion of the  
DB input and its associated inverter function dramatically  
increases the number of combinatorial functions that can  
be implemented in a single module from 800 options in  
previous architectures to more than 4,000 in the SX  
architecture. An example of the improved flexibility  
enabled by the inversion capability is the ability to  
integrate a 3-input exclusive-OR function into a single  
C-cell. This facilitates construction of 9-bit parity-tree  
functions with 2 ns propagation delays. At the same  
time, the C-cell structure is extremely synthesis friendly,  
simplifying the overall design and reducing synthesis  
time.  
1-2  
v3.2  
SX Family FPGAs  
To increase design efficiency and device performance,  
Actel has further organized these modules into  
SuperClusters (Figure 1-4). SuperCluster 1 is a two-wide  
grouping of Type 1 clusters. SuperCluster 2 is a two-wide  
group containing one Type 1 cluster and one Type 2  
cluster. SX devices feature more SuperCluster 1 modules  
than SuperCluster 2 modules because designers typically  
require significantly more combinatorial logic than flip-  
flops.  
Chip Architecture  
The SX family chip architecture provides a unique  
approach to module organization and chip routing that  
delivers the best register/logic mix for a wide variety of  
new and emerging applications.  
Module Organization  
Actel has arranged all C-cell and R-cell logic modules into  
horizontal banks called clusters. There are two types of  
clusters: Type 1 contains two C-cells and one R-cell, while  
Type 2 contains one C-cell and two R-cells.  
D0  
D1  
Y
D2  
D3  
Sb  
Sa  
DB  
A0 B0  
A1 B1  
Figure 1-3 C-Cell  
C-Cell  
R-Cell  
D0  
D1  
Routed Data Input  
S1  
S0  
PSETB  
CLRB  
Y
D2  
Direct  
Connect  
Input  
D3  
D
Q
Y
Sa  
Sb  
HCLK  
CLKA, CLKB,  
Internal Logic  
DB  
CKS  
CKP  
A0 B0  
A1 B1  
Cluster 1  
Cluster 2  
Cluster 2  
Cluster 1  
Type 1 SuperCluster  
Type 2 SuperCluster  
Figure 1-4 Cluster Organization  
v3.2  
1-3  
SX Family FPGAs  
Routing Resources  
Clusters and SuperClusters can be connected through the use of two innovative local routing resources called  
FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within  
clusters and SuperClusters (Figure 1-5 and Figure 1-6). This routing architecture also dramatically reduces the number  
of antifuses required to complete a circuit, ensuring the highest possible performance.  
DirectConnect  
• No antifuses  
• 0.1 ns routing delay  
FastConnect  
• One antifuse  
• 0.4 ns routing delay  
Routing Segments  
• Typically 2 antifuses  
• Max. 5 antifuses  
Figure 1-5 DirectConnect and FastConnect for Type 1 SuperClusters  
DirectConnect  
• No antifuses  
• 0.1 ns routing delay  
FastConnect  
• One antifuse  
• 0.4 ns routing delay  
Routing Segments  
• Typically 2 antifuses  
• Max. 5 antifuses  
Figure 1-6 DirectConnect and FastConnect for Type 2 SuperClusters  
1-4  
v3.2  
SX Family FPGAs  
DirectConnect is a horizontal routing resource that  
provides connections from a C-cell to its neighboring R-  
cell in a given SuperCluster. DirectConnect uses a  
hardwired signal path requiring no programmable  
interconnection to achieve its fast signal propagation  
time of less than 0.1 ns.  
Performance  
The combination of architectural features described  
above enables SX devices to operate with internal clock  
frequencies exceeding 300 MHz, enabling very fast  
execution of even complex logic functions. Thus, the SX  
family is an optimal platform upon which to integrate  
the functionality previously contained in multiple CPLDs.  
In addition, designs that previously would have required  
a gate array to meet performance goals can now be  
integrated into an SX device with dramatic  
improvements in cost and time to market. Using timing-  
driven place-and-route tools, designers can achieve  
highly deterministic device performance. With SX  
devices, designers do not need to use complicated  
performance-enhancing design techniques such as the  
use of redundant logic to reduce fanout on critical nets  
or the instantiation of macros in HDL code to achieve  
high performance.  
FastConnect enables horizontal routing between any  
two logic modules within a given SuperCluster and  
vertical routing with the SuperCluster immediately  
below it. Only one programmable connection is used in a  
FastConnect path, delivering maximum pin-to-pin  
propagation of 0.4 ns.  
In addition to DirectConnect and FastConnect, the  
architecture makes use of two globally oriented routing  
resources known as segmented routing and high-drive  
routing. The Actel segmented routing structure provides  
a variety of track lengths for extremely fast routing  
between SuperClusters. The exact combination of track  
lengths and antifuses within each path is chosen by the  
100 percent automatic place-and-route software to  
minimize signal propagation delays.  
I/O Modules  
Each I/O on an SX device can be configured as an input,  
an output, a tristate output, or a bidirectional pin.  
The Actel high-drive routing structure provides three  
clock networks. The first clock, called HCLK, is hardwired  
from the HCLK buffer to the clock select multiplexer  
(MUX) in each R-cell. This provides a fast propagation  
path for the clock signal, enabling the 3.7 ns clock-to-out  
(pin-to-pin) performance of the SX devices. The  
hardwired clock is tuned to provide clock skew as low as  
0.25 ns. The remaining two clocks (CLKA, CLKB) are  
global clocks that can be sourced from external pins or  
from internal logic signals within the SX device.  
Even without the inclusion of dedicated I/O registers,  
these I/Os, in combination with array registers, can  
achieve clock-to-out (pad-to-pad) timing as fast as 3.7 ns.  
I/O cells that have embedded latches and flip-flops  
require instantiation in HDL code; this is a design  
complication not encountered in SX FPGAs. Fast pin-to-  
pin timing ensures that the device will have little trouble  
interfacing with any other device in the system, which in  
turn enables parallel design of system components and  
reduces overall design time.  
Other Architectural Features  
Technology  
The Actel SX family is implemented on a high-voltage  
twin-well CMOS process using 0.35 µ design rules. The  
metal-to-metal antifuse is made up of a combination of  
amorphous silicon and dielectric material with barrier  
metals and has a programmed ("on" state) resistance of  
25 Ω with a capacitance of 1.0 fF for low signal impedance.  
Power Requirements  
The SX family supports 3.3 V operation and is designed  
to tolerate 5.0 V inputs. (Table 1-1). Power consumption  
is extremely low due to the very short distances signals  
are required to travel to complete a circuit. Power  
requirements are further reduced because of the small  
number of low-resistance antifuses in the path. The  
antifuse architecture does not require active circuitry to  
hold a charge (as do SRAM or EPROM), making it the  
lowest power architecture on the market.  
Table 1-1 Supply Voltages  
Device  
VCCA  
VCCI  
VCCR  
Maximum Input Tolerance  
Maximum Output Drive  
A54SX08  
A54SX16  
A54SX32  
3.3 V  
3.3 V  
5.0 V  
5.0 V  
3.3 V  
A54SX16-P*  
3.3 V  
3.3 V  
3.3 V  
3.3 V  
3.3 V  
5.0 V  
3.3 V  
5.0 V  
5.0 V  
3.3 V  
5.0 V  
5.0 V  
3.3 V  
3.3 V  
5.0 V  
Note: *A54SX16-P has three different entries because it is capable of both a 3.3 V and a 5.0 V drive.  
v3.2  
1-5  
SX Family FPGAs  
Boundary Scan Testing (BST)  
Development Tool Support  
The SX family of FPGAs is fully supported by both the  
Actel Libero® Integrated Design Environment (IDE) and  
Designer FPGA Development software. Actel Libero IDE  
All SX devices are IEEE 1149.1 compliant. SX devices offer  
superior diagnostic and testing capabilities by providing  
Boundary Scan Testing (BST) and probing capabilities.  
These functions are controlled through the special test  
pins in conjunction with the program fuse. The  
functionality of each pin is described in Table 1-2. In the  
dedicated test mode, TCK, TDI, and TDO are dedicated  
pins and cannot be used as regular I/Os. In flexible mode,  
TMS should be set HIGH through a pull-up resistor of  
10 kΩ. TMS can be pulled LOW to initiate the test  
sequence.  
is  
a
design management environment, seamlessly  
integrating design tools while guiding the user through  
the design flow, managing all design and log files, and  
passing necessary design data among tools. Libero IDE  
allows users to integrate both schematic and HDL  
synthesis into a single flow and verify the entire design  
in a single environment. Libero IDE includes Synplify® for  
Actel from Synplicity®, ViewDraw® for Actel from  
Mentor Graphics®, ModelSim® HDL Simulator from  
The program fuse determines whether the device is in  
dedicated or flexible mode. The default (fuse not blown)  
is flexible mode.  
Mentor  
Graphics,  
WaveFormer  
Lite™  
from  
SynaptiCAD™, and Designer software from Actel. Refer  
to the Libero IDE flow diagram (located on the Actel  
website) for more information.  
Table 1-2 Boundary Scan Pin Functionality  
Actel Designer software is a place-and-route tool and  
provides a comprehensive suite of backend support tools  
for FPGA development. The Designer software includes  
Program Fuse Blown  
(Dedicated Test Mode)  
Program Fuse Not Blown  
(Flexible Mode)  
TCK, TDI, TDO are dedicated TCK, TDI, TDO are flexible and  
BST pins. may be used as I/Os.  
timing-driven place-and-route, and  
a
world-class  
integrated static timing analyzer and constraints editor.  
With the Designer software, a user can select and lock  
package pins while only minimally impacting the results  
of place-and-route. Additionally, the back-annotation  
flow is compatible with all the major simulators, and the  
simulation results can be cross-probed with Silicon  
Explorer II, Actel integrated verification and logic  
analysis tool. Another tool included in the Designer  
software is the SmartGen core generator, which easily  
creates popular and commonly used logic functions for  
implementation into your schematic or HDL design. Actel  
Designer software is compatible with the most popular  
FPGA design entry and verification tools from companies  
such as Mentor Graphics, Synplicity, Synopsys®, and  
Cadence® Design Systems. The Designer software is  
available for both the Windows® and UNIX® operating  
systems.  
No need for pull-up resistor for Use a pull-up resistor of 10 kΩ  
TMS  
on TMS.  
Dedicated Test Mode  
In Dedicated mode, all JTAG pins are reserved for BST;  
designers cannot use them as regular I/Os. An internal  
pull-up resistor is automatically enabled on both TMS  
and TDI pins, and the TMS pin will function as defined in  
the IEEE 1149.1 (JTAG) specification.  
To select Dedicated mode, users need to reserve the JTAG  
pins in Actel's Designer software by checking the  
"Reserve JTAG" box in "Device Selection Wizard"  
(Figure 1-7). JTAG pins comply with LVTTL/TTL I/O  
specification regardless of whether they are used as a  
user I/O or a JTAG I/O. Refer to the Table 1-5 on page 1-8  
for detailed specifications.  
Probe Circuit Control Pins  
The Silicon Explorer II tool uses the boundary scan ports  
(TDI, TCK, TMS, and TDO) to select the desired nets for  
verification. The selected internal nets are assigned to  
the PRA/PRB pins for observation. Figure 1-8 on page 1-7  
illustrates the interconnection between Silicon Explorer II  
and the FPGA to perform in-circuit verification.  
Design Considerations  
The TDI, TCK, TDO, PRA, and PRB pins should not be used  
as input or bidirectional ports. Because these pins are  
active during probing, critical signals input through  
these pins are not available while probing. In addition,  
the Security Fuse should not be programmed because  
doing so disables the Probe Circuitry.  
Figure 1-7 Device Selection Wizard  
1-6  
v3.2  
SX Family FPGAs  
16 Channels  
SX FPGA  
TDI  
TCK  
TMS  
Silicon  
Explorer II  
Serial Connection  
TDO  
PRA  
PRB  
Figure 1-8 Probe Setup  
The procedure for programming an SX device using  
Silicon Sculptor II are as follows:  
Programming  
Device programming is supported through Silicon  
Sculptor series of programmers. In particular, Silicon  
Sculptor II are compact, robust, single-site and multi-site  
device programmer for the PC.  
1. Load the .AFM file  
2. Select the device to be programmed  
3. Begin programming  
When the design is ready to go to production, Actel  
offers device volume-programming services either  
through distribution partners or via in-house  
programming from the factory.  
With standalone software, Silicon Sculptor II allows  
concurrent programming of multiple units from the  
same PC, ensuring the fastest programming times  
possible. Each fuse is subsequently verified by Silicon  
Sculptor II to insure correct programming. In addition,  
integrity tests ensure that no extra fuses are  
programmed. Silicon Sculptor II also provides extensive  
hardware self-testing capability.  
For more details on programming SX devices, refer to the  
Programming Antifuse Devices application note and the  
Silicon Sculptor II User's Guide.  
3.3 V / 5 V Operating Conditions  
Table 1-3 Absolute Maximum Ratings1  
Symbol  
Parameter  
Limits  
Units  
2
VCCR  
DC Supply Voltage3  
DC Supply Voltage  
–0.3 to + 6.0  
–0.3 to + 4.0  
–0.3 to + 4.0  
–0.3 to + 6.0  
–0.5 to + 5.5  
–0.5 to + 3.6  
–30 to + 5.0  
–65 to +150  
V
V
2
VCCA  
2
VCCI  
DC Supply Voltage (A54SX08, A54SX16, A54SX32)  
DC Supply Voltage (A54SX16P)  
Input Voltage  
V
2
VCCI  
V
VI  
V
VO  
Output Voltage  
V
IIO  
I/O Source Sink Current3  
mA  
°C  
TSTG  
Notes:  
Storage Temperature  
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute  
maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the  
Recommended Operating Conditions.  
2. VCCR in the A54SX16P must be greater than or equal to VCCI during power-up and power-down sequences and during normal  
operation.  
3. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC  
0.5 V or less than GND – 0.5 V, the internal protection diodes will forward-bias and can draw excessive current.  
+
v3.2  
1-7  
SX Family FPGAs  
Table 1-4 Recommended Operating Conditions  
Parameter  
Commercial  
0 to + 70  
±10  
Industrial  
–40 to + 85  
±10  
Military  
–55 to +125  
±10  
Units  
°C  
Temperature Range*  
3.3 V Power Supply Tolerance  
5.0 V Power Supply Tolerance  
%VCC  
%VCC  
±5  
±10  
±10  
Note: *Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military.  
Table 1-5 Electrical Specifications  
Commercial  
Industrial  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Units  
VOH  
(IOH = –20 µA) (CMOS)  
(IOH = –8 mA) (TTL)  
(IOH = –6 mA) (TTL)  
(VCCI – 0.1)  
2.4  
VCCI  
VCCI  
(VCCI – 0.1)  
VCCI  
V
2.4  
VCCI  
VOL  
(IOL= 20 µA) (CMOS)  
(IOL = 12 mA) (TTL)  
(IOL = 8 mA) (TTL)  
0.10  
0.50  
V
0.50  
0.8  
VIL  
0.8  
V
V
VIH  
2.0  
2.0  
tR, tF  
CIO  
Input Transition Time tR, tF  
CIO I/O Capacitance  
50  
10  
50  
10  
ns  
pF  
mA  
ICC  
Standby Current, ICC  
4.0  
4.0  
ICC(D)  
ICC(D) Dynamic  
I
VCC Supply Current  
See "Evaluating Power in SX Devices" on page 1-16.  
1-8  
v3.2  
SX Family FPGAs  
PCI Compliance for the SX Family  
The SX family supports 3.3 V and 5.0 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.  
Table 1-6 A54SX16P DC Specifications (5.0 V PCI Operation)  
Symbol  
VCCA  
VCCR  
VCCI  
VIH  
Parameter  
Condition  
Min.  
3.0  
Max.  
3.6  
Units  
V
Supply Voltage for Array  
Supply Voltage required for Internal Biasing  
Supply Voltage for I/Os  
Input High Voltage1  
4.75  
4.75  
2.0  
5.25  
5.25  
VCC + 0.5  
0.8  
V
V
V
VIL  
Input Low Voltage1  
–0.5  
V
IIH  
Input High Leakage Current  
Input Low Leakage Current  
Output High Voltage  
VIN = 2.7  
70  
µA  
µA  
V
IIL  
VIN = 0.5  
–70  
VOH  
VOL  
IOUT = –2 mA  
IOUT = 3 mA, 6 mA  
2.4  
5
Output Low Voltage2  
0.55  
10  
12  
8
V
CIN  
Input Pin Capacitance3  
pF  
pF  
pF  
CCLK  
CIDSEL  
Notes:  
CLK Pin Capacitance  
IDSEL Pin Capacitance4  
1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.  
2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter include,  
FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used, AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and  
ACK64#.  
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).  
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].  
v3.2  
1-9  
SX Family FPGAs  
A54SX16P AC Specifications for (PCI Operation)  
Table 1-7 A54SX16P AC Specifications for (PCI Operation)  
Symbol  
Parameter  
Condition  
Min.  
–44  
Max.  
Units  
mA  
IOH(AC)  
Switching Current High  
0 < VOUT 1.41  
1.4 VOUT < 2.41, 2  
–44 + (VOUT – 1.4)/0.024  
mA  
1, 3  
3.1 < VOUT < VCC  
EQ 1-1 on page 1-11  
–142  
(Test Point)  
VOUT = 3.13  
mA  
mA  
IOL(AC)  
Switching Current High  
VOUT 2.21  
95  
2.2 > VOUT > 0.551  
0.71 > VOUT > 01, 3  
VOUT = 0.713  
VOUT/0.023  
EQ 1-2 on page 1-11  
206  
mA  
mA  
(Test Point)  
ICL  
Low Clamp Current  
Output Rise Slew Rate  
Output Fall Slew Rate  
–5 < VIN –1  
–25 + (VIN + 1) /0.015  
mA  
slewR  
slewF  
Notes:  
0.4 V to 2.4 V load4  
2.4 V to 0.4 V load4  
1
1
5
5
V/ns  
V/ns  
1. Refer to the V/I curves in Figure 1-9 on page 1-11. Switching current characteristics for REQ# and GNT# are permitted to be one half  
of that specified here; i.e., half-size output drivers may be used on these signals. This specification does not apply to CLK and RST#,  
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,  
which are open drain outputs.  
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than  
toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.  
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A  
and B) are provided with the respective diagrams in Figure 1-9 on page 1-11. The equation defined maxima should be met by  
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.  
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any  
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter  
with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum  
parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not  
required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates;  
therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur, and should  
ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.  
Pin  
1/2 in. max.  
Output  
Buffer  
VCC  
10 pF  
1 kΩ  
1 kΩ  
1-10  
v3.2  
SX Family FPGAs  
Figure 1-9 shows the 5.0 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P  
device.  
0.50  
0.45  
0.40  
PCI IOL Maximum  
0.35  
0.30  
0.25  
SX PCI IOL  
0.20  
0.15  
0.10  
PCI IOL Mininum  
0.05  
0
1
2
3
4
5
6
–0.05  
–0.10  
–0.15  
–0.20  
PCI IOH Mininum  
SX PCI IOH  
PCI IOH Maximum  
Voltage Out  
Figure 1-9 5.0 V PCI Curve for A54SX16P Device  
IOH = 11.9 × (VOUT – 5.25) × (VOUT + 2.45)  
for VCC > VOUT > 3.1 V  
IOL = 78.5 × VOUT × (4.4 – VOUT  
for 0 V < VOUT < 0.71 V  
)
EQ 1-1  
EQ 1-2  
v3.2  
1-11  
SX Family FPGAs  
A54SX16P DC Specifications (3.3 V PCI Operation)  
Table 1-8 A54SX16P DC Specifications (3.3 V PCI Operation)  
Symbol  
VCCA  
VCCR  
VCCI  
VIH  
Parameter  
Condition  
Min.  
3.0  
Max.  
3.6  
Units  
V
Supply Voltage for Array  
Supply Voltage required for Internal Biasing  
Supply Voltage for I/Os  
Input High Voltage  
3.0  
3.6  
V
3.0  
3.6  
V
0.5VCC  
–0.5  
VCC + 0.5  
0.3VCC  
V
VIL  
Input Low Voltage  
V
IIPU  
Input Pull-up Voltage1  
Input Leakage Current2  
Output High Voltage  
Output Low Voltage  
0.7VCC  
V
IIL  
0 < VIN < VCC  
IOUT = –500 µA  
IOUT = 1500 µA  
10  
µA  
V
VOH  
0.9VCC  
VOL  
0.1VCC  
V
CIN  
Input Pin Capacitance3  
CLK Pin Capacitance  
IDSEL Pin Capacitance4  
10  
12  
8
pF  
pF  
pF  
CCLK  
CIDSEL  
Notes:  
5
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a  
floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current  
at this input voltage.  
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.  
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).  
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].  
1-12  
v3.2  
SX Family FPGAs  
A54SX16P AC Specifications (3.3 V PCI Operation)  
Table 1-9 A54SX16P AC Specifications (3.3 V PCI Operation)  
Symbol Parameter  
Switching Current High  
Condition  
Min.  
Max.  
Units  
mA  
1
0 < VOUT 0.3VCC  
1
0.3VCC VOUT < 0.9VCC  
–12VCC  
mA  
IOH(AC)  
1, 2  
0.7VCC < VOUT < VCC  
–17.1 + (VCC – VOUT  
)
EQ 1-3 on page 1-14  
–32VCC  
2
(Test Point)  
VOUT = 0.7VCC  
mA  
mA  
mA  
1
Switching Current High  
VCC > VOUT 0.6VCC  
1
0.6VCC > VOUT > 0.1VCC  
0.18VCC > VOUT > 01, 2  
16VCC  
IOL(AC)  
26.7VOUT  
EQ 1-4 on page 1-14 mA  
2
(Test Point)  
VOUT = 0.18VCC  
38VCC  
ICL  
Low Clamp Current  
High Clamp Current  
Output Rise Slew Rate3  
Output Fall Slew Rate3  
–3 < VIN –1  
–25 + (VIN + 1)/0.015  
mA  
ICH  
–3 < VIN –1  
25 + (VIN – VOUT – 1)/0.015  
mA  
slewR  
slewF  
Notes:  
0.2VCC to 0.6VCC load  
0.6VCC to 0.2VCC load  
1
1
4
4
V/ns  
V/ns  
1. Refer to the V/I curves in Figure 1-10 on page 1-14. Switching current characteristics for REQ# and GNT# are permitted to be  
one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to  
CLK and RST# which are system outputs. “Switching Current High” specification are not relevant to SERR#, INTA#, INTB#,  
INTC#, and INTD# which are open drain outputs.  
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums  
(C and D) are provided with the respective diagrams in Figure 1-10 on page 1-14. The equation defined maxima should be  
met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output  
driver.  
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate  
at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet  
this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both  
maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply  
to open drain outputs.  
Pin  
1/2 in. max.  
Output  
Buffer  
VCC  
10 pF  
1 kΩ  
1 kΩ  
v3.2  
1-13  
SX Family FPGAs  
Figure 1-10 shows the 3.3 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P  
device.  
0.50  
0.45  
0.40  
PCI IOL Maximum  
0.35  
0.30  
0.25  
0.20  
SX PCI IOL  
0.15  
0.10  
PCI IOL Minimum  
0.05  
SX PCI IOH  
0
1
2
3
4
5
6
–0.05  
–0.10  
–0.15  
–0.20  
PCI IOH Minimum  
PCI IOH Maximum  
Voltage Out  
Figure 1-10 3.3 V PCI Curve for A54SX16P Device  
IOH = (98.0/VCC) × (VOUT – VCC) × (VOUT + 0.4VCC  
for VCC > VOUT > 0.7 VCC  
)
IOL = (256/VCC) × VOUT × (VCC – VOUT  
)
for 0 V < VOUT < 0.18 VCC  
EQ 1-3  
EQ 1-4  
1-14  
v3.2  
SX Family FPGAs  
Power-Up Sequencing  
Table 1-10 Power-Up Sequencing  
VCCA  
VCCR  
VCCI  
Power-Up Sequence  
Comments  
A54SX08, A54SX16, A54SX32  
3.3 V  
5.0 V  
3.3 V  
5.0 V First  
3.3 V Second  
No possible damage to device  
Possible damage to device  
3.3 V First  
5.0 V Second  
A54SX16P  
3.3 V  
3.3 V  
5.0 V  
3.3 V  
3.3 V  
3.3 V Only  
No possible damage to device  
No possible damage to device  
3.3 V  
5.0 V First  
3.3 V Second  
3.3 V First  
5.0 V Second  
Possible damage to device  
No possible damage to device  
No possible damage to device  
3.3 V  
5.0 V  
5.0 V  
5.0 V First  
3.3 V Second  
3.3 V First  
5.0 V Second  
Note: No inputs should be driven (high or low) before completion of power-up.  
Power-Down Sequencing  
Table 1-11 Power-Down Sequencing  
VCCA  
VCCR  
VCCI  
Power-Down Sequence  
Comments  
A54SX08, A54SX16, A54SX32  
3.3 V  
5.0 V  
3.3 V  
5.0 V First  
Possible damage to device  
3.3 V Second  
3.3 V First  
No possible damage to device  
5.0 V Second  
A54SX16P  
3.3 V  
3.3 V  
5.0 V  
3.3 V  
3.3 V  
3.3 V Only  
No possible damage to device  
Possible damage to device  
3.3 V  
5.0 V First  
3.3 V Second  
3.3 V First  
5.0 V Second  
No possible damage to device  
No possible damage to device  
No possible damage to device  
3.3 V  
5.0 V  
5.0 V  
5.0 V First  
3.3 V Second  
3.3 V First  
5.0 V Second  
Note: No inputs should be driven (high or low) after the beginning of the power-down sequence.  
v3.2  
1-15  
SX Family FPGAs  
AC Power Dissipation  
Evaluating Power in SX Devices  
The power dissipation of the SX Family is usually  
dominated by the dynamic power dissipation. Dynamic  
power dissipation is a function of frequency, equivalent  
capacitance, and power supply voltage. The AC power  
dissipation is defined in EQ 1-7 and EQ 1-8.  
A critical element of system reliability is the ability of  
electronic devices to safely dissipate the heat generated  
during operation. The thermal characteristics of a circuit  
depend on the device and package used, the operating  
temperature, the operating current, and the system's  
ability to dissipate heat.  
PAC = PModule + PRCLKA Net + PRCLKB Net + PHCLK Net  
Output Buffer + PInput Buffer  
+
P
You should complete a power evaluation early in the  
design process to help identify potential heat-related  
problems in the system and to prevent the system from  
exceeding the device’s maximum allowed junction  
temperature.  
EQ 1-7  
PAC = VCCA2 × [(m × CEQM × fm)Module  
(n × CEQI × fn)Input Buffer+ (p × (CEQO + CL) × fp)Output Buffer  
(0.5 × (q1 × CEQCR × fq1) + (r1 × fq1))RCLKA  
(0.5 × (q2 × CEQCR × fq2)+ (r2 × fq2))RCLKB +  
+
+
+
The actual power dissipated by most applications is  
significantly lower than the power the package can  
(0.5 × (s1 × CEQHV × fs1) + (CEQHF × fs1))HCLK  
]
dissipate. However,  
a thermal analysis should be  
EQ 1-8  
performed for all projects. To perform  
evaluation, follow these steps:  
a power  
Definition of Terms Used in Formula  
1. Estimate the power consumption of the  
application.  
m
=
=
=
=
Number of logic modules switching at fm  
n
Number of input buffers switching at fn  
Number of output buffers switching at fp  
Number of clock loads on the first routed array  
clock  
2. Calculate the maximum power allowed for the  
device and package.  
p
q1  
3. Compare the estimated power and maximum  
power values.  
q2  
=
Number of clock loads on the second routed array  
clock  
x
=
=
=
=
Number of I/Os at logic low  
Estimating Power Consumption  
y
Number of I/Os at logic high  
The total power dissipation for the SX family is the sum  
of the DC power dissipation and the AC power  
dissipation. Use EQ 1-5 to calculate the estimated power  
consumption of your application.  
r1  
r2  
Fixed capacitance due to first routed array clock  
Fixed capacitance due to second routed array  
clock  
s1  
=
Number of clock loads on the dedicated array  
clock  
PTotal = PDC + PAC  
CEQM  
CEQI  
CEQO  
CEQCR  
CEQHV  
CEQHF  
CL  
fm  
fn  
fp  
fq1  
=
=
=
=
=
=
=
=
=
=
=
=
=
Equivalent capacitance of logic modules in pF  
Equivalent capacitance of input buffers in pF  
Equivalent capacitance of output buffers in pF  
Equivalent capacitance of routed array clock in pF  
Variable capacitance of dedicated array clock  
Fixed capacitance of dedicated array clock  
Output lead capacitance in pF  
EQ 1-5  
DC Power Dissipation  
The power due to standby current is typically a small  
component of the overall power. The Standby power is  
shown in Table 1-12 for commercial, worst-case  
conditions (70°C).  
Table 1-12 Standby Power  
Average logic module switching rate in MHz  
Average input buffer switching rate in MHz  
Average output buffer switching rate in MHz  
Average first routed array clock rate in MHz  
Average second routed array clock rate in MHz  
Average dedicated array clock rate in MHz  
ICC  
VCC  
Power  
4 mA  
3.6 V  
14.4 mW  
fq2  
fs1  
The DC power dissipation is defined in EQ 1-6.  
PDC = (Istandby) × VCCA + (Istandby) × VCCR  
(Istandby) × VCCI + xVOL × IOL + y(VCCI – VOH) × VOH  
+
EQ 1-6  
1-16  
v3.2  
SX Family FPGAs  
Table 1-13 shows capacitance values for various  
devices.  
Guidelines for Calculating Power  
Consumption  
The power consumption guidelines are meant to  
represent worst-case scenarios so that they can be  
generally used to predict the upper limits of power  
dissipation. These guidelines are shown in Table 1-14.  
Table 1-13 Capacitance Values for Devices  
A54SX08 A54SX16 A54SX16P A54SX32  
CEQM (pF)  
CEQI (pF)  
CEQO (pF)  
CEQCR (pF)  
CEQHV  
4.0  
3.4  
4.7  
1.6  
0.615  
60  
4.0  
3.4  
4.0  
3.4  
4.0  
3.4  
4.7  
4.7  
4.7  
Sample Power Calculation  
1.6  
1.6  
1.6  
One of the designs used to characterize the SX family  
was a 528 bit serial-in, serial-out shift register. The design  
utilized 100 percent of the dedicated flip-flops of an  
A54SX16P device. A pattern of 0101… was clocked into  
the device at frequencies ranging from 1 MHz to  
200 MHz. Shifting in a series of 0101… caused 50 percent  
of the flip-flops to toggle from low to high at every clock  
cycle.  
0.615  
96  
0.615  
96  
0.615  
140  
171  
171  
CEQHF  
r1 (pF)  
87  
138  
138  
138  
138  
r2 (pF)  
87  
Table 1-14 Power Consumption Guidelines  
Description  
Power Consumption Guideline  
Logic Modules (m)  
20% of modules  
Inputs Switching (n)  
# inputs/4  
Outputs Switching (p)  
# outputs/4  
First Routed Array Clock Loads (q1)  
Second Routed Array Clock Loads (q2)  
Load Capacitance (CL)  
20% of register cells  
20% of register cells  
35 pF  
Average Logic Module Switching Rate (fm)  
Average Input Switching Rate (fn)  
Average Output Switching Rate (fp)  
f/10  
f/5  
f/10  
Average First Routed Array Clock Rate (fq1  
Average Second Routed Array Clock Rate (fq2  
Average Dedicated Array Clock Rate (fs1)  
Dedicated Clock Array Clock Loads (s1)  
)
f/2  
)
f/2  
f
20% of regular modules  
Follow the steps below to estimate power consumption.  
The values provided for the sample calculation below are  
for the shift register design above. This method for  
estimating power consumption is conservative and the  
actual power consumption of your design may be less  
than the estimated power consumption.  
AC Power Dissipation  
PAC = PModule + PRCLKA Net + PRCLKB Net + PHCLK Net  
POutput Buffer + PInput Buffer  
+
EQ 1-10  
PAC = VCCA2 × [(m × CEQM × fm)Module  
(n × CEQI × fn)Input Buffer+ (p × (CEQO + CL) × fp)Output Buffer  
(0.5 (q1 × CEQCR × fq1) + (r1 × fq1))RCLKA  
(0.5 (q2 × CEQCR × fq2)+ (r2 × fq2))RCLKB  
(0.5 (s1 × CEQHV × fs1) + (CEQHF × fs1))HCLK  
+
The total power dissipation for the SX family is the sum  
of the AC power dissipation and the DC power  
dissipation.  
+
+
+
]
PTotal = PAC (dynamic power) + PDC (static power)  
EQ 1-9  
EQ 1-11  
v3.2  
1-17  
SX Family FPGAs  
Step 1: Define Terms Used in Formula  
Step 2: Calculate Dynamic Power Consumption  
VCCA  
3.3  
VCCA × VCCA  
10.89  
0.02112  
0.000136  
0.000794  
0.11208  
0
Module  
m × fm × CEQM  
Number of logic modules switching  
at fm (Used 50%)  
m
264  
20  
n × fn × CEQI  
p × fp × (CEQO+CL)  
0.5 (q1 × CEQCR × fq1) + (r1 × fq1  
Average logic modules switching rate  
fm  
)
fm (MHz) (Guidelines: f/10)  
0.5(q2 × CEQCR × fq2) + (r2 × fq2  
)
Module capacitance CEQM (pF)  
Input Buffer  
CEQM 4.0  
0.5 (s1 × CEQHV × fs1) + (CEQHF × fs1)  
PAC = 1.461 W  
0
Number of input buffers switching at fn  
n
1
Step 3: Calculate DC Power Dissipation  
DC Power Dissipation  
Average input switching rate fn (MHz)  
(Guidelines: f/5)  
fn  
40  
PDC = (Istandby) × VCCA + (Istandby) × VCCR + (Istandby) ×  
VCCI + X × VOL × IOL + Y(VCCI – VOH) × VOH  
Input buffer capacitance CEQI (pF)  
Output Buffer  
CEQI  
3.4  
EQ 1-12  
Number of output buffers switching at fp  
p
1
For a rough estimate of DC Power Dissipation, only use  
PDC = (Istandby) × VCCA. The rest of the formula provides a  
very small number that can be considered negligible.  
Average output buffers switching rate  
fp(MHz) (Guidelines: f/10)  
fp  
20  
Output buffers buffer capacitance  
CEQO (pF)  
CEQO 4.7  
PDC = (Istandby) × VCCA  
PDC = .55 mA × 3.3 V  
PDC = 0.001815 W  
Output Load capacitance CL (pF)  
RCLKA  
CL  
q1  
35  
Number of Clock loads q1  
Capacitance of routed array clock (pF)  
Average clock rate (MHz)  
Fixed capacitance (pF)  
RCLKB  
528  
Step 4: Calculate Total Power Consumption  
CEQCR 1.6  
PTotal = PAC + PDC  
fq1  
r1  
200  
138  
PTotal = 1.461 + 0.001815  
P
Total = 1.4628 W  
Step 5: Compare Estimated Power Consumption  
against Characterized Power Consumption  
The estimated total power consumption for this design is  
1.46 W. The characterized power consumption for this  
design at 200 MHz is 1.0164 W.  
Number of Clock loads q2  
Capacitance of routed array clock (pF)  
Average clock rate (MHz)  
Fixed capacitance (pF)  
HCLK  
q2  
0
CEQCR 1.6  
fq2  
r2  
0
138  
Number of Clock loads  
s1  
0
Variable capacitance of dedicated  
array clock (pF)  
CEQHV 0.61  
5
Fixed capacitance of dedicated  
array clock (pF)  
CEQHF 96  
Average clock rate (MHz)  
fs1  
0
1-18  
v3.2  
SX Family FPGAs  
Figure 1-11 shows the characterized power dissipation numbers for the shift register design using frequencies ranging  
from 1 MHz to 200 MHz.  
1200  
1000  
800  
600  
400  
200  
0
0
20  
40  
60  
80  
100  
120  
140  
160  
180  
200  
Frequency MHz  
Figure 1-11 Power Dissipation  
P
= Power calculated from Estimating Power  
Consumption section  
Junction Temperature (T )  
J
The temperature that you select in Designer Series  
software is the junction temperature, not ambient  
temperature. This is an important distinction because the  
heat generated from dynamic power consumption is  
usually hotter than the ambient temperature. Use the  
equation below to calculate junction temperature.  
θ
= Junction to ambient of package. θ numbers are  
ja  
ja  
located in the "Package Thermal Characteristics"  
section.  
Package Thermal Characteristics  
The device junction to case thermal characteristic is θjc,  
and the junction to ambient air characteristic is θja. The  
thermal characteristics for θja are shown with two  
different air flow rates.  
Junction Temperature = ΔT + Ta  
EQ 1-13  
Where:  
The maximum junction temperature is 150 °C.  
Ta = Ambient Temperature  
A sample calculation of the absolute maximum power  
dissipation allowed for a TQFP 176-pin package at  
commercial temperature and still air is as follows:  
ΔT = Temperature gradient between junction (silicon)  
and ambient  
ΔT = θja × P  
Max. junction temp. (°C) – Max. ambient temp. (°C)  
150°C – 70°C  
Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------ = ----------------------------------- = 2 . 86 W  
θja (°C/W)  
28°C/W  
EQ 1-14  
v3.2  
1-19  
SX Family FPGAs  
Table 1-15 Package Thermal Characteristics  
θja  
Still Air  
θja  
Package Type  
Pin Count  
84  
θjc  
12  
11  
11  
10  
8
300 ft/min.  
Units  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Plastic Leaded Chip Carrier (PLCC)  
Thin Quad Flat Pack (TQFP)  
32  
32  
22  
24  
144  
Thin Quad Flat Pack (TQFP)  
176  
28  
21  
Very Thin Quad Flatpack (VQFP)  
Plastic Quad Flat Pack (PQFP) without Heat Spreader  
Plastic Quad Flat Pack (PQFP) with Heat Spreader  
Plastic Ball Grid Array (PBGA)  
100  
38  
32  
208  
30  
23  
208  
3.8  
3
20  
17  
272  
20  
14.5  
17  
Plastic Ball Grid Array (PBGA)  
313  
3
23  
Plastic Ball Grid Array (PBGA)  
329  
3
18  
13.5  
26.7  
Fine Pitch Ball Grid Array (FBGA)  
Note: SX08 does not have a heat spreader.  
144  
3.8  
38.8  
Table 1-16 Temperature and Voltage Derating Factors*  
Junction Temperature  
VCCA  
3.0  
–55  
0.75  
0.70  
0.66  
–40  
0.78  
0.73  
0.69  
0
25  
70  
85  
125  
1.16  
1.08  
1.02  
0.87  
0.82  
0.77  
0.89  
0.83  
0.78  
1.00  
0.93  
0.87  
1.04  
0.97  
0.92  
3.3  
3.6  
Note: *Normalized to worst-case commercial, TJ = 70°C, VCCA = 3.0 V  
1-20  
v3.2  
SX Family FPGAs  
SX Timing Model  
Input Delays  
Output Delays  
I/O Module  
Predicted  
Routing  
Delays  
Internal Delays  
I/O Module  
tINY = 1.5 ns  
Combinatorial Cell  
tIRD2 = 0.6 ns  
tDHL = 1.6 ns  
t
RD1 = 0.3 ns  
tPD = 0.6 ns  
tRD4 = 1.0 ns  
t
RD8 = 1.9 ns  
I/O Module  
DLH = 1.6 ns  
t
Register Cell  
Register Cell  
D
Q
D
Q
tRD1 = 0.3 ns  
tRD1 = 0.3 ns  
tENZH = 2.3 ns  
t
t
SUD = 0.5 ns  
HD = 0.0 ns  
tRCO = 0.8 ns  
t
RCO = 0.8 ns  
Routed  
Clock  
tRCKH = 1.5 ns (100% Load)  
FMAX = 250 MHz  
Hardwired  
Clock  
tHCKH = 1.0 ns  
FHMAX = 320 MHz  
Note: Values shown for A54SX08-3, worst-case commercial conditions.  
Figure 1-12 SX Timing Model  
Hardwired Clock  
Routed Clock  
External Setup = tINY + tIRD1 + tSUD – tHCKH  
External Setup = tINY + tIRD1 + tSUD – tRCKH  
= 1.5 + 0.3 + 0.5 – 1.0 = 1.3 ns  
= 1.5 + 0.3 + 0.5 – 1.5 = 0.8 ns  
EQ 1-15  
EQ 1-16  
EQ 1-17  
EQ 1-18  
Clock-to-Out (Pin-to-Pin)  
Clock-to-Out (Pin-to-Pin)  
= tHCKH + tRCO + tRD1 + tDHL  
= 1.0 + 0.8 + 0.3 + 1.6 = 3.7 ns  
= tRCKH + tRCO + tRD1 + tDHL  
= 1.52+ 0.8 + 0.3 + 1.6 = 4.2 ns  
v3.2  
1-21  
SX Family FPGAs  
E
D
To AC Test Loads (shown below)  
PAD  
TRIBUFF  
VCC  
V
VCC  
50%  
CC  
GND  
GND  
En  
In  
GND  
1.5 V  
50% 50%  
En  
50% 50%  
VOH  
50%  
VCC  
VOH  
1.5 V  
Out  
VOL  
90%  
Out  
10%  
1.5 V  
Out  
GND  
1.5 V  
VOL  
tDLH  
tDHL  
tENZH  
tENHZ  
tENLZ  
tENZL  
Figure 1-13 Output Buffer Delays  
Load 2  
(used to measure  
disable delays)  
Load 2  
(used to measure  
enable delays)  
Load 1  
(used to measure  
propagation delay)  
VCC  
VCC  
GND  
GND  
To Output  
Under Test  
35 pF  
R to V  
R to GND for tPHZ  
R = 1 kΩ  
for tPLZ  
R to VCC for tPLZ  
R to GND for tPHZ  
R = 1 kΩ  
CC  
To Output  
Under Test  
To Output  
Under Test  
35 pF  
35 pF  
Figure 1-14 AC Test Loads  
S
A
B
Y
Y
PA D  
INBUF  
VCC  
S, A ,or B  
GND  
50%  
50% 50%  
VCC  
3 V  
1.5 V 1.5 V  
VCC  
Out  
50%  
0 V  
50%  
In  
GND  
tPD  
t
PD  
VCC  
50%  
Out  
GND  
Out  
50%  
50%  
tPD  
GND  
tPD  
tINY  
tINY  
Figure 1-15 Input Buffer Delays  
Figure 1-16 C-Cell Delays  
1-22  
v3.2  
SX Family FPGAs  
Register Cell Timing Characteristics  
Q
PRESET  
CLR  
D
CLK  
(positive edge triggered)  
tHD  
D
tHP  
tSUD  
tHPWH'  
RPWH  
CLK  
tHPWL  
RPWL  
'
tRCO  
Q
tPRESET  
tCLR  
CLR  
tWASYN  
PRESET  
Figure 1-17 Flip-Flops  
Long Tracks  
Timing Characteristics  
Some nets in the design use long tracks. Long tracks are  
special routing resources that span multiple rows,  
columns, or modules. Long tracks employ three and  
sometimes five antifuse connections. This increases  
capacitance and resistance, resulting in longer net delays  
for macros connected to long tracks. Typically up to 6  
percent of nets in a fully utilized device require long  
tracks. Long tracks contribute approximately 4 ns to 8.4  
ns delay. This additional delay is represented statistically  
in higher fanout (FO = 24) routing delays in the  
datasheet specifications section.  
Timing characteristics for SX devices fall into three  
categories: family-dependent, device-dependent, and  
design-dependent. The input and output buffer  
characteristics are common to all SX family members.  
Internal routing delays are device-dependent. Design  
dependency means actual delays are not determined  
until after placement and routing of the user’s design is  
complete. Delay values may then be determined by using  
the DirectTime Analyzer utility or performing simulation  
with post-layout delays.  
Critical Nets and Typical Nets  
Timing Derating  
Propagation delays are expressed only for typical nets,  
which are used for initial design performance evaluation.  
Critical net delays can then be applied to the most time-  
critical paths. Critical nets are determined by net  
property assignment prior to placement and routing. Up  
to 6% of the nets in a design may be designated as  
critical, while 90% of the nets in a design are typical.  
SX devices are manufactured in a CMOS process.  
Therefore, device performance varies according to  
temperature, voltage, and process variations. Minimum  
timing parameters reflect maximum operating voltage,  
minimum operating temperature, and best-case  
processing. Maximum timing parameters reflect  
minimum operating voltage, maximum operating  
temperature, and worst-case processing.  
v3.2  
1-23  
SX Family FPGAs  
A54SX08 Timing Characteristics  
Table 1-17 A54SX08 Timing Characteristics  
(Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C)  
'–3' Speed '–2' Speed '–1' Speed  
Min. Max. Min. Max. Min. Max. Min. Max. Units  
'Std' Speed  
Parameter Description  
C-Cell Propagation Delays1  
tPD  
Internal Array Module  
0.6  
0.7  
0.8  
0.9  
ns  
Predicted Routing Delays2  
tDC  
FO = 1 Routing Delay, Direct Connect  
0.1  
0.3  
0.3  
0.6  
0.8  
1.0  
1.9  
2.8  
0.1  
0.4  
0.4  
0.7  
0.9  
1.2  
2.2  
3.2  
0.1  
0.4  
0.4  
0.8  
1.0  
1.4  
2.5  
3.7  
0.1  
0.5  
0.5  
0.9  
1.2  
1.6  
2.9  
4.3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tFC  
FO = 1 Routing Delay, Fast Connect  
FO = 1 Routing Delay  
tRD1  
tRD2  
FO = 2 Routing Delay  
tRD3  
FO = 3 Routing Delay  
tRD4  
FO = 4 Routing Delay  
tRD8  
FO = 8 Routing Delay  
tRD12  
R-Cell Timing  
tRCO  
FO = 12 Routing Delay  
Sequential Clock-to-Q  
0.8  
0.5  
0.7  
1.1  
0.6  
0.8  
1.2  
0.7  
0.9  
1.4  
0.8  
1.0  
ns  
ns  
ns  
ns  
ns  
ns  
tCLR  
Asynchronous Clear-to-Q  
Asynchronous Preset-to-Q  
Flip-Flop Data Input Set-Up  
Flip-Flop Data Input Hold  
Asynchronous Pulse Width  
tPRESET  
tSUD  
0.5  
0.0  
1.4  
0.5  
0.0  
1.6  
0.7  
0.0  
1.8  
0.8  
0.0  
2.1  
tHD  
tWASYN  
Input Module Propagation Delays  
tINYH  
Input Data Pad-to-Y HIGH  
1.5  
1.5  
1.7  
1.7  
1.9  
1.9  
2.2  
2.2  
ns  
ns  
tINYL  
Input Data Pad-to-Y LOW  
Input Module Predicted Routing Delays2  
tIRD1  
tIRD2  
tIRD3  
tIRD4  
tIRD8  
tIRD12  
Note:  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
FO = 12 Routing Delay  
0.3  
0.6  
0.8  
1.0  
1.9  
2.8  
0.4  
0.7  
0.9  
1.2  
2.2  
3.2  
0.4  
0.8  
1.0  
1.4  
2.5  
3.7  
0.5  
0.9  
1.2  
1.6  
2.9  
4.3  
ns  
ns  
ns  
ns  
ns  
ns  
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route  
timing is based on actual routing delay measurements performed on the device prior to shipment.  
1-24  
v3.2  
SX Family FPGAs  
Table 1-17 A54SX08 Timing Characteristics (Continued)  
(Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C)  
'–3' Speed  
'–2' Speed  
'–1' Speed  
'Std' Speed  
Parameter Description  
Min. Max. Min. Max. Min. Max. Min. Max. Units  
Dedicated (Hardwired) Array Clock Network  
tHCKH  
tHCKL  
tHPWH  
tHPWL  
tHCKSW  
tHP  
Input LOW to HIGH (pad to R-Cell input)  
Input HIGH to LOW (pad to R-Cell input)  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
1.0  
1.0  
1.1  
1.2  
1.3  
1.4  
1.5  
1.6  
ns  
ns  
1.4  
1.4  
1.6  
1.6  
1.8  
1.8  
2.1  
2.1  
ns  
ns  
0.1  
0.2  
0.2  
0.2  
ns  
Minimum Period  
2.7  
3.1  
3.6  
4.2  
ns  
fHMAX  
Maximum Frequency  
350  
320  
280  
240  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (light load)  
(pad to R-Cell input)  
1.3  
1.4  
1.4  
1.5  
1.5  
1.5  
1.5  
1.6  
1.7  
1.7  
1.7  
1.8  
1.7  
1.8  
1.9  
2.0  
1.9  
2.0  
2.0  
2.1  
2.2  
2.3  
2.2  
2.3  
ns  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (light load)  
(pad to R-Cell Input)  
Input LOW to HIGH (50% load)  
(pad to R-Cell input)  
Input HIGH to LOW (50% load)  
(pad to R-Cell input)  
Input LOW to HIGH (100% load)  
(pad to R-Cell input)  
Input HIGH to LOW (100% load)  
(pad to R-Cell input)  
tRPWH  
Min. Pulse Width HIGH  
2.1  
2.1  
2.4  
2.4  
2.7  
2.7  
3.2  
3.2  
ns  
ns  
ns  
ns  
ns  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Maximum Skew (light load)  
Maximum Skew (50% load)  
Maximum Skew (100% load)  
0.1  
0.3  
0.3  
0.2  
0.3  
0.3  
0.2  
0.4  
0.4  
0.2  
0.4  
0.4  
TTL Output Module Timing1  
tDLH  
Data-to-Pad LOW to HIGH  
1.6  
1.6  
2.1  
2.3  
1.4  
1.9  
1.9  
2.4  
2.7  
1.7  
2.1  
2.1  
2.8  
3.1  
1.9  
2.5  
2.5  
3.2  
3.6  
2.2  
ns  
ns  
ns  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Enable-to-Pad, Z to L  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
tENZL  
tENZH  
tENLZ  
Note:  
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route  
timing is based on actual routing delay measurements performed on the device prior to shipment.  
v3.2  
1-25  
SX Family FPGAs  
A54SX16 Timing Characteristics  
Table 1-18 A54SX16 Timing Characteristics  
(Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C)  
'–3' Speed '–2' Speed '–1' Speed  
Min. Max. Min. Max. Min. Max. Min. Max. Units  
'Std' Speed  
Parameter Description  
C-Cell Propagation Delays1  
tPD  
Internal Array Module  
0.6  
0.7  
0.8  
0.9  
ns  
Predicted Routing Delays2  
tDC  
FO = 1 Routing Delay, Direct Connect  
0.1  
0.3  
0.3  
0.6  
0.8  
1.0  
1.9  
2.8  
0.1  
0.4  
0.4  
0.7  
0.9  
1.2  
2.2  
3.2  
0.1  
0.4  
0.4  
0.8  
1.0  
1.4  
2.5  
3.7  
0.1  
0.5  
0.5  
0.9  
1.2  
1.6  
2.9  
4.3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tFC  
FO = 1 Routing Delay, Fast Connect  
FO = 1 Routing Delay  
tRD1  
tRD2  
FO = 2 Routing Delay  
tRD3  
FO = 3 Routing Delay  
tRD4  
FO = 4 Routing Delay  
tRD8  
FO = 8 Routing Delay  
tRD12  
R-Cell Timing  
tRCO  
FO = 12 Routing Delay  
Sequential Clock-to-Q  
0.8  
0.5  
0.7  
1.1  
0.6  
0.8  
1.2  
0.7  
0.9  
1.4  
0.8  
1.0  
ns  
ns  
ns  
ns  
ns  
ns  
tCLR  
Asynchronous Clear-to-Q  
Asynchronous Preset-to-Q  
Flip-Flop Data Input Set-Up  
Flip-Flop Data Input Hold  
Asynchronous Pulse Width  
tPRESET  
tSUD  
0.5  
0.0  
1.4  
0.5  
0.0  
1.6  
0.7  
0.0  
1.8  
0.8  
0.0  
2.1  
tHD  
tWASYN  
Input Module Propagation Delays  
tINYH  
Input Data Pad-to-Y HIGH  
1.5  
1.5  
1.7  
1.7  
1.9  
1.9  
2.2  
2.2  
ns  
ns  
tINYL  
Input Data Pad-to-Y LOW  
Predicted Input Routing Delays2  
tIRD1  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
FO = 12 Routing Delay  
0.3  
0.6  
0.8  
1.0  
1.9  
2.8  
0.4  
0.7  
0.9  
1.2  
2.2  
3.2  
0.4  
0.8  
1.0  
1.4  
2.5  
3.7  
0.5  
0.9  
1.2  
1.6  
2.9  
4.3  
ns  
ns  
ns  
ns  
ns  
ns  
tIRD2  
tIRD3  
tIRD4  
tIRD8  
tIRD12  
Notes:  
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route  
timing is based on actual routing delay measurements performed on the device prior to shipment.  
3. Delays based on 35 pF loading, except tENZL and tENZH. For tENZL and tENZH, the loading is 5 pF.  
1-26  
v3.2  
SX Family FPGAs  
Table 1-18 A54SX16 Timing Characteristics (Continued)  
(Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C)  
'–3' Speed  
'–2' Speed  
'–1' Speed  
'Std' Speed  
Parameter Description  
Min. Max. Min. Max. Min. Max. Min. Max. Units  
Dedicated (Hardwired) Array Clock Network  
tHCKH  
tHCKL  
tHPWH  
tHPWL  
tHCKSW  
tHP  
Input LOW to HIGH (pad to R-Cell input)  
Input HIGH to LOW (pad to R-Cell input)  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
1.2  
1.2  
1.4  
1.4  
1.5  
1.6  
1.8  
1.9  
ns  
ns  
1.4  
1.4  
1.6  
1.6  
1.8  
1.8  
2.1  
2.1  
ns  
ns  
0.2  
0.2  
0.3  
0.3  
ns  
Minimum Period  
2.7  
3.1  
3.6  
4.2  
ns  
fHMAX  
Maximum Frequency  
350  
320  
280  
240  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (light load)  
(pad to R-Cell input)  
1.6  
1.8  
1.8  
2.0  
1.8  
2.0  
1.8  
2.0  
2.1  
2.2  
2.1  
2.2  
2.1  
2.3  
2.5  
2.5  
2.4  
2.5  
2.5  
2.7  
2.8  
3.0  
2.8  
3.0  
ns  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (light load)  
(pad to R-Cell input)  
Input LOW to HIGH (50% load)  
(pad to R-Cell input)  
Input HIGH to LOW (50% load)  
(pad to R-Cell input)  
Input LOW to HIGH (100% load)  
(pad to R-Cell input)  
Input HIGH to LOW (100% load)  
(pad to R-Cell input)  
tRPWH  
Min. Pulse Width HIGH  
2.1  
2.1  
2.4  
2.4  
2.7  
2.7  
3.2  
3.2  
ns  
ns  
ns  
ns  
ns  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Maximum Skew (light load)  
Maximum Skew (50% load)  
Maximum Skew (100% load)  
0.5  
0.5  
0.5  
0.5  
0.6  
0.6  
0.5  
0.7  
0.7  
0.7  
0.8  
0.8  
TTL Output Module Timing3  
tDLH  
Data-to-Pad LOW to HIGH  
1.6  
1.6  
2.1  
2.3  
1.4  
1.3  
1.9  
1.9  
2.4  
2.7  
1.7  
1.5  
2.1  
2.1  
2.8  
3.1  
1.9  
1.7  
2.5  
2.5  
3.2  
3.6  
2.2  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Enable-to-Pad, Z to L  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
Enable-to-Pad, H to Z  
tENZL  
tENZH  
tENLZ  
tENHZ  
Notes:  
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route  
timing is based on actual routing delay measurements performed on the device prior to shipment.  
3. Delays based on 35 pF loading, except tENZL and tENZH. For tENZL and tENZH, the loading is 5 pF.  
v3.2  
1-27  
SX Family FPGAs  
A54SX16P Timing Characteristics  
Table 1-19 A54SX16P Timing Characteristics  
(Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C)  
'–3' Speed '–2' Speed '–1' Speed  
Min. Max. Min. Max. Min. Max. Min. Max. Units  
'Std' Speed  
Parameter Description  
C-Cell Propagation Delays1  
tPD  
Internal Array Module  
0.6  
0.7  
0.8  
0.9  
ns  
Predicted Routing Delays2  
tDC  
FO = 1 Routing Delay, Direct Connect  
0.1  
0.3  
0.3  
0.6  
0.8  
1.0  
1.9  
2.8  
0.1  
0.4  
0.4  
0.7  
0.9  
1.2  
2.2  
3.2  
0.1  
0.4  
0.4  
0.8  
1.0  
1.4  
2.5  
3.7  
0.1  
0.5  
0.5  
0.9  
1.2  
1.6  
2.9  
4.3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tFC  
FO = 1 Routing Delay, Fast Connect  
FO = 1 Routing Delay  
tRD1  
tRD2  
FO = 2 Routing Delay  
tRD3  
FO = 3 Routing Delay  
tRD4  
FO = 4 Routing Delay  
tRD8  
FO = 8 Routing Delay  
tRD12  
R-Cell Timing  
tRCO  
FO = 12 Routing Delay  
Sequential Clock-to-Q  
0.9  
0.5  
0.7  
1.1  
0.6  
0.8  
1.3  
0.7  
0.9  
1.4  
0.8  
1.0  
ns  
ns  
ns  
ns  
ns  
ns  
tCLR  
Asynchronous Clear-to-Q  
Asynchronous Preset-to-Q  
Flip-Flop Data Input Set-Up  
Flip-Flop Data Input Hold  
Asynchronous Pulse Width  
tPRESET  
tSUD  
0.5  
0.0  
1.4  
0.5  
0.0  
1.6  
0.7  
0.0  
1.8  
0.8  
0.0  
2.1  
tHD  
tWASYN  
Input Module Propagation Delays  
tINYH  
Input Data Pad-to-Y HIGH  
1.5  
1.5  
1.7  
1.7  
1.9  
1.9  
2.2  
2.2  
ns  
ns  
tINYL  
Input Data Pad-to-Y LOW  
Predicted Input Routing Delays2  
tIRD1  
tIRD2  
tIRD3  
tIRD4  
tIRD8  
tIRD12  
Note:  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
FO = 12 Routing Delay  
0.3  
0.6  
0.8  
1.0  
1.9  
2.8  
0.4  
0.7  
0.9  
1.2  
2.2  
3.2  
0.4  
0.8  
1.0  
1.4  
2.5  
3.7  
0.5  
0.9  
1.2  
1.6  
2.9  
4.3  
ns  
ns  
ns  
ns  
ns  
ns  
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route  
timing is based on actual routing delay measurements performed on the device prior to shipment.  
3. Delays based on 10 pF loading.  
1-28  
v3.2  
SX Family FPGAs  
Table 1-19 A54SX16P Timing Characteristics (Continued)  
(Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C)  
'–3' Speed  
'–2' Speed  
'–1' Speed  
'Std' Speed  
Parameter Description  
Min. Max. Min. Max. Min. Max. Min. Max. Units  
Dedicated (Hardwired) Array Clock Network  
tHCKH  
tHCKL  
tHPWH  
tHPWL  
tHCKSW  
tHP  
Input LOW to HIGH (pad to R-Cell input)  
Input HIGH to LOW (pad to R-Cell input)  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
1.2  
1.2  
1.4  
1.4  
1.5  
1.6  
1.8  
1.9  
ns  
ns  
1.4  
1.4  
1.6  
1.6  
1.8  
1.8  
2.1  
2.1  
ns  
ns  
0.2  
0.2  
0.3  
0.3  
ns  
Minimum Period  
2.7  
3.1  
3.6  
4.2  
ns  
fHMAX  
Maximum Frequency  
350  
320  
280  
240  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (light load)  
(pad to R-Cell input)  
1.6  
1.8  
1.8  
2.0  
1.8  
2.0  
1.8  
2.0  
2.1  
2.2  
2.1  
2.2  
2.1  
2.3  
2.5  
2.5  
2.4  
2.5  
2.5  
2.7  
2.8  
3.0  
2.8  
3.0  
ns  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (Light Load)  
(pad to R-Cell input)  
Input LOW to HIGH (50% load)  
(pad to R-Cell input)  
Input HIGH to LOW (50% load)  
(pad to R-Cell input)  
Input LOW to HIGH (100% load)  
(pad to R-Cell input)  
Input HIGH to LOW (100% load)  
(pad to R-Cell input)  
tRPWH  
Min. Pulse Width HIGH  
2.1  
2.1  
2.4  
2.4  
2.7  
2.7  
3.2  
3.2  
ns  
ns  
ns  
ns  
ns  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Maximum Skew (light load)  
Maximum Skew (50% load)  
Maximum Skew (100% load)  
0.5  
0.5  
0.5  
0.5  
0.6  
0.6  
0.5  
0.7  
0.7  
0.7  
0.8  
0.8  
TTL Output Module Timing  
tDLH  
Data-to-Pad LOW to HIGH  
2.4  
2.3  
3.0  
3.3  
2.3  
2.8  
2.8  
2.9  
3.4  
3.8  
2.7  
3.2  
3.1  
3.2  
3.9  
4.3  
3.0  
3.7  
3.7  
3.8  
4.6  
5.0  
3.5  
4.3  
ns  
ns  
ns  
ns  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Enable-to-Pad, Z to L  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
Enable-to-Pad, H to Z  
tENZL  
tENZH  
tENLZ  
tENHZ  
Note:  
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route  
timing is based on actual routing delay measurements performed on the device prior to shipment.  
3. Delays based on 10 pF loading.  
v3.2  
1-29  
SX Family FPGAs  
Table 1-19 A54SX16P Timing Characteristics (Continued)  
(Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C)  
'–3' Speed  
'–2' Speed  
'–1' Speed  
'Std' Speed  
Parameter Description  
Min. Max. Min. Max. Min. Max. Min. Max. Units  
TTL/PCI Output Module Timing  
tDLH  
Data-to-Pad LOW to HIGH  
Data-to-Pad HIGH to LOW  
Enable-to-Pad, Z to L  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
Enable-to-Pad, H to Z  
1.5  
1.9  
2.3  
1.5  
2.7  
2.9  
1.7  
2.2  
2.6  
1.7  
3.1  
3.3  
2.0  
2.4  
3.0  
1.9  
3.5  
3.7  
2.3  
2.9  
3.5  
2.3  
4.1  
4.4  
ns  
ns  
ns  
ns  
ns  
ns  
tDHL  
tENZL  
tENZH  
tENLZ  
tENHZ  
PCI Output Module Timing3  
tDLH  
Data-to-Pad LOW to HIGH  
1.8  
1.7  
0.8  
1.2  
1.0  
1.1  
2.0  
2.0  
1.0  
1.2  
1.1  
1.3  
2.3  
2.2  
1.1  
1.5  
1.3  
1.5  
2.7  
2.6  
1.3  
1.8  
1.5  
1.7  
ns  
ns  
ns  
ns  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Enable-to-Pad, Z to L  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
Enable-to-Pad, H to Z  
tENZL  
tENZH  
tENLZ  
tENHZ  
TTL Output Module Timing  
tDLH  
Data-to-Pad LOW to HIGH  
2.1  
2.0  
2.5  
3.0  
2.3  
2.9  
2.5  
2.3  
2.9  
3.5  
2.7  
3.3  
2.8  
2.6  
3.2  
3.9  
3.1  
3.7  
3.3  
3.1  
3.8  
4.6  
3.6  
4.4  
ns  
ns  
ns  
ns  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Enable-to-Pad, Z to L  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
Enable-to-Pad, H to Z  
tENZL  
tENZH  
tENLZ  
tENHZ  
Note:  
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route  
timing is based on actual routing delay measurements performed on the device prior to shipment.  
3. Delays based on 10 pF loading.  
1-30  
v3.2  
SX Family FPGAs  
A54SX32 Timing Characteristics  
Table 1-20 A54SX32 Timing Characteristics  
(Worst-Case Commercial Conditions, VCCR= 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C)  
'–3' Speed '–2' Speed '–1' Speed  
Min. Max. Min. Max. Min. Max. Min. Max. Units  
'Std' Speed  
Parameter Description  
C-Cell Propagation Delays1  
tPD  
Internal Array Module  
0.6  
0.7  
0.8  
0.9  
ns  
Predicted Routing Delays2  
tDC  
FO = 1 Routing Delay, Direct Connect  
0.1  
0.3  
0.3  
0.7  
1.0  
1.4  
2.7  
4.0  
0.1  
0.4  
0.4  
0.8  
1.2  
1.6  
3.1  
4.7  
0.1  
0.4  
0.4  
0.9  
1.4  
1.8  
3.5  
5.3  
0.1  
0.5  
0.5  
1.0  
1.6  
2.1  
4.1  
6.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tFC  
FO = 1 Routing Delay, Fast Connect  
FO = 1 Routing Delay  
tRD1  
tRD2  
FO = 2 Routing Delay  
tRD3  
FO = 3 Routing Delay  
tRD4  
FO = 4 Routing Delay  
tRD8  
FO = 8 Routing Delay  
tRD12  
R-Cell Timing  
tRCO  
FO = 12 Routing Delay  
Sequential Clock-to-Q  
0.8  
0.5  
0.7  
1.1  
0.6  
0.8  
1.3  
0.7  
0.9  
1.4  
0.8  
1.0  
ns  
ns  
ns  
ns  
ns  
ns  
tCLR  
Asynchronous Clear-to-Q  
Asynchronous Preset-to-Q  
Flip-Flop Data Input Set-Up  
Flip-Flop Data Input Hold  
Asynchronous Pulse Width  
tPRESET  
tSUD  
0.5  
0.0  
1.4  
0.6  
0.0  
1.6  
0.7  
0.0  
1.8  
0.8  
0.0  
2.1  
tHD  
tWASYN  
Input Module Propagation Delays  
tINYH  
Input Data Pad-to-Y HIGH  
1.5  
1.5  
1.7  
1.7  
1.9  
1.9  
2.2  
2.2  
ns  
ns  
tINYL  
Input Data Pad-to-Y LOW  
Predicted Input Routing Delays2  
tIRD1  
tIRD2  
tIRD3  
tIRD4  
tIRD8  
tIRD12  
Note:  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
FO = 12 Routing Delay  
0.3  
0.7  
1.0  
1.4  
2.7  
4.0  
0.4  
0.8  
1.2  
1.6  
3.1  
4.7  
0.4  
0.9  
1.4  
1.8  
3.5  
5.3  
0.5  
1.0  
1.6  
2.1  
4.1  
6.2  
ns  
ns  
ns  
ns  
ns  
ns  
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route  
timing is based on actual routing delay measurements performed on the device prior to shipment.  
3. Delays based on 35 pF loading, except tENZL and tENZH. For tENZL and tENZH the loading is 5 pF.  
v3.2  
1-31  
SX Family FPGAs  
Table 1-20 A54SX32 Timing Characteristics (Continued)  
(Worst-Case Commercial Conditions, VCCR= 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C)  
'–3' Speed  
'–2' Speed  
'–1' Speed  
'Std' Speed  
Parameter Description  
Min. Max. Min. Max. Min. Max. Min. Max. Units  
Dedicated (Hardwired) Array Clock Network  
tHCKH  
tHCKL  
tHPWH  
tHPWL  
tHCKSW  
tHP  
Input LOW to HIGH (pad to R-Cell input)  
Input HIGH to LOW (pad to R-Cell input)  
Minimum Pulse Width HIGH  
Minimum Pulse Width LOW  
Maximum Skew  
1.9  
1.9  
2.1  
2.1  
2.4  
2.4  
2.8  
2.8  
ns  
ns  
1.4  
1.4  
1.6  
1.6  
1.8  
1.8  
2.1  
2.1  
ns  
ns  
0.3  
0.4  
0.4  
0.5  
ns  
Minimum Period  
2.7  
3.1  
3.6  
4.2  
ns  
fHMAX  
Maximum Frequency  
350  
320  
280  
240  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
tRCKH  
tRCKL  
Input LOW to HIGH (light load)  
(pad to R-Cell input)  
2.4  
2.4  
2.7  
2.7  
2.7  
2.8  
2.7  
2.7  
3.0  
3.1  
3.1  
3.2  
3.0  
3.1  
3.5  
3.6  
3.5  
3.6  
3.5  
3.6  
4.1  
4.2  
4.1  
4.3  
ns  
ns  
ns  
ns  
ns  
ns  
Input HIGH to LOW (light load)  
(pad to R-Cell input)  
Input LOW to HIGH (50% load)  
(pad to R-Cell input)  
Input HIGH to LOW (50% load)  
(pad to R-Cell input)  
Input LOW to HIGH (100% load)  
(pad to R-Cell input)  
Input HIGH to LOW (100% load)  
(pad to R-Cell input)  
tRPWH  
Min. Pulse Width HIGH  
2.1  
2.1  
2.4  
2.4  
2.7  
2.7  
3.2  
3.2  
ns  
ns  
ns  
ns  
ns  
tRPWL  
Min. Pulse Width LOW  
tRCKSW  
tRCKSW  
tRCKSW  
Maximum Skew (light load)  
Maximum Skew (50% load)  
Maximum Skew (100% load)  
0.85  
1.23  
1.30  
0.98  
1.4  
1.1  
1.6  
1.7  
1.3  
1.9  
2.0  
1.5  
TTL Output Module Timing3  
tDLH  
Data-to-Pad LOW to HIGH  
1.6  
1.6  
2.1  
2.3  
1.4  
1.3  
1.9  
1.9  
2.4  
2.7  
1.7  
1.5  
2.1  
2.1  
2.8  
3.1  
1.9  
1.7  
2.5  
2.5  
3.2  
3.6  
2.2  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
tDHL  
Data-to-Pad HIGH to LOW  
Enable-to-Pad, Z to L  
Enable-to-Pad, Z to H  
Enable-to-Pad, L to Z  
Enable-to-Pad, H to Z  
tENZL  
tENZH  
tENLZ  
tENHZ  
Note:  
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating  
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route  
timing is based on actual routing delay measurements performed on the device prior to shipment.  
3. Delays based on 35 pF loading, except tENZL and tENZH. For tENZL and tENZH the loading is 5 pF.  
1-32  
v3.2  
SX Family FPGAs  
Pin Description  
CLKA/B  
Clock A and B  
TCK  
Test Clock  
These pins are 3.3 V / 5.0 V PCI/TTL clock inputs for clock  
distribution networks. The clock input is buffered prior  
to clocking the R-cells. If not used, this pin must be set  
LOW or HIGH on the board. It must not be left floating.  
(For A54SX72A, these clocks can be configured as  
bidirectional.)  
Test clock input for diagnostic probe and device  
programming. In flexible mode, TCK becomes active  
when the TMS pin is set LOW (refer to Table 1-2 on  
page 1-6). This pin functions as an I/O when the  
boundary scan state machine reaches the "logic reset"  
state.  
GND  
Ground  
TDI  
Test Data Input  
LOW supply voltage.  
Serial input for boundary scan testing and diagnostic  
probe. In flexible mode, TDI is active when the TMS pin is  
set LOW (refer to Table 1-2 on page 1-6). This pin  
functions as an I/O when the boundary scan state  
machine reaches the "logic reset" state.  
HCLK  
Dedicated (hardwired) Array Clock  
This pin is the 3.3 V / 5.0 V PCI/TTL clock input for sequential  
modules. This input is directly wired to each R-cell and  
offers clock speeds independent of the number of R-cells  
being driven. If not used, this pin must be set LOW or  
HIGH on the board. It must not be left floating.  
TDO  
Test Data Output  
Serial output for boundary scan testing. In flexible mode,  
TDO is active when the TMS pin is set LOW (refer to  
Table 1-2 on page 1-6). This pin functions as an I/O when  
the boundary scan state machine reaches the “logic  
reset” state.  
I/O  
Input/Output  
The I/O pin functions as an input, output, tristate, or  
bidirectional buffer. Based on certain configurations,  
input and output levels are compatible with standard  
TTL, LVTTL, 3.3 V PCI or 5.0 V PCI specifications. Unused  
I/O pins are automatically tristated by the Designer Series  
software.  
TMS  
Test Mode Select  
The TMS pin controls the use of the IEEE 1149.1  
Boundary Scan pins (TCK, TDI, TDO). In flexible mode  
when the TMS pin is set LOW, the TCK, TDI, and TDO pins  
are boundary scan pins (refer to Table 1-2 on page 1-6).  
Once the boundary scan pins are in test mode, they will  
remain in that mode until the internal boundary scan  
state machine reaches the "logic reset" state. At this  
point, the boundary scan pins will be released and will  
function as regular I/O pins. The "logic reset" state is  
reached 5 TCK cycles after the TMS pin is set HIGH. In  
dedicated test mode, TMS functions as specified in the  
IEEE 1149.1 specifications.  
NC  
No Connection  
This pin is not connected to circuitry within the device.  
PRA, I/O  
Probe A  
The Probe A pin is used to output data from any user-  
defined design node within the device. This independent  
diagnostic pin can be used in conjunction with the Probe  
B pin to allow real-time diagnostic output of any signal  
path within the device. The Probe A pin can be used as a  
user-defined I/O when verification has been completed.  
The pin’s probe capabilities can be permanently disabled  
to protect programmed design confidentiality.  
V
Supply Voltage  
CCI  
Supply voltage for I/Os. See Table 1-1 on page 1-5.  
PRB, I/O  
Probe B  
V
Supply Voltage  
CCA  
The Probe B pin is used to output data from any node  
within the device. This diagnostic pin can be used in  
conjunction with the Probe A pin to allow real-time  
diagnostic output of any signal path within the device.  
The Probe B pin can be used as a user-defined I/O when  
verification has been completed. The pin’s probe  
capabilities can be permanently disabled to protect  
programmed design confidentiality.  
Supply voltage for Array. See Table 1-1 on page 1-5.  
V
Supply Voltage  
CCR  
Supply voltage for input tolerance (required for internal  
biasing). See Table 1-1 on page 1-5.  
v3.2  
1-33  
54SX Family FPGAs  
Package Pin Assignments  
84-Pin PLCC  
1
84  
84-Pin  
PLCC  
Figure 2-1 84-Pin PLCC (Top View)  
Note  
For Package Manufacturing and Environmental information, visit the Package Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
v3.2  
2-1  
54SX Family FPGAs  
84-Pin PLCC  
84-Pin PLCC  
A54SX08  
84-Pin PLCC  
A54SX08  
A54SX08  
Function  
Pin Number  
Pin Number  
Function  
Pin Number  
Function  
1
VCCR  
GND  
VCCA  
PRA, I/O  
I/O  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
I/O  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
I/O  
2
I/O  
I/O  
3
I/O  
I/O  
4
I/O  
I/O  
5
PRB, I/O  
VCCA  
GND  
VCCR  
I/O  
I/O  
6
I/O  
I/O  
7
VCCI  
I/O  
I/O  
8
I/O  
9
I/O  
I/O  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
I/O  
HCLK  
I/O  
I/O  
TCK, I/O  
TDI, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CLKA  
CLKB  
I/O  
I/O  
I/O  
I/O  
TMS  
I/O  
I/O  
TDO, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
VCCI  
GND  
I/O  
I/O  
I/O  
GND  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
GND  
I/O  
I/O  
I/O  
2-2  
v3.2  
54SX Family FPGAs  
208-Pin PQFP  
208  
1
208-Pin PQFP  
Figure 2-2 208-Pin PQFP (Top View)  
Note  
For Package Manufacturing and Environmental information, visit the Package Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
v3.2  
2-3  
54SX Family FPGAs  
208-Pin PQFP  
A54SX16,  
208-Pin PQFP  
A54SX16,  
A54SX08  
A54SX16P  
Function  
A54SX32  
Function  
A54SX08  
Function  
A54SX16P  
Function  
A54SX32  
Function  
Pin Number  
Function  
GND  
TDI, I/O  
I/O  
Pin Number  
37  
1
GND  
TDI, I/O  
I/O  
GND  
TDI, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
VCCA  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
VCCA  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
NC*  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
2
38  
3
39  
NC  
VCCI  
VCCA  
I/O  
4
NC  
I/O  
I/O  
40  
5
I/O  
I/O  
I/O  
41  
6
NC  
I/O  
I/O  
42  
7
I/O  
I/O  
I/O  
43  
I/O  
8
I/O  
I/O  
I/O  
44  
I/O  
9
I/O  
I/O  
I/O  
45  
I/O  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
I/O  
I/O  
I/O  
46  
I/O  
TMS  
VCCI  
I/O  
TMS  
VCCI  
I/O  
TMS  
VCCI  
I/O  
47  
I/O  
48  
NC  
I/O  
49  
NC  
I/O  
I/O  
50  
NC  
I/O  
I/O  
I/O  
I/O  
51  
I/O  
I/O  
I/O  
52  
GND  
I/O  
NC  
I/O  
I/O  
53  
I/O  
I/O  
I/O  
54  
I/O  
I/O  
I/O  
I/O  
55  
I/O  
NC  
I/O  
I/O  
56  
I/O  
I/O  
I/O  
I/O  
57  
I/O  
I/O  
I/O  
I/O  
58  
I/O  
NC  
I/O  
I/O  
59  
I/O  
I/O  
I/O  
I/O  
60  
VCCI  
NC  
I/O  
VCCR  
GND  
VCCA  
GND  
I/O  
VCCR  
GND  
VCCA  
GND  
I/O  
VCCR  
GND  
VCCA  
GND  
I/O  
61  
62  
63  
I/O  
64  
NC  
I/O  
65*  
66  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
67  
NC  
I/O  
I/O  
I/O  
I/O  
68  
I/O  
I/O  
I/O  
69  
I/O  
I/O  
I/O  
I/O  
70  
NC  
I/O  
NC  
I/O  
I/O  
71  
I/O  
I/O  
I/O  
72  
I/O  
Note: * Note that Pin 65 in the A54SX32—PQ208 is a no connect (NC).  
2-4  
v3.2  
54SX Family FPGAs  
208-Pin PQFP  
A54SX16,  
208-Pin PQFP  
A54SX16,  
A54SX08  
Function  
A54SX16P  
Function  
A54SX32  
Function  
A54SX08  
Function  
A54SX16P  
Function  
A54SX32  
Function  
Pin Number  
73  
Pin Number  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
74  
I/O  
75  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
76  
PRB, I/O  
GND  
VCCA  
GND  
VCCR  
I/O  
PRB, I/O  
GND  
VCCA  
GND  
VCCR  
I/O  
PRB, I/O  
GND  
VCCA  
GND  
VCCR  
I/O  
I/O  
I/O  
I/O  
77  
I/O  
I/O  
I/O  
78  
VCCA  
VCCI  
NC  
VCCA  
VCCI  
I/O  
VCCA  
VCCI  
I/O  
79  
80  
81  
I/O  
I/O  
I/O  
82  
HCLK  
I/O  
HCLK  
I/O  
HCLK  
I/O  
I/O  
I/O  
I/O  
83  
NC  
I/O  
I/O  
84  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
85  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
86  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
87  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
88  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
89  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
90  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
91  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
92  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
93  
I/O  
I/O  
I/O  
GND  
VCCA  
GND  
VCCR  
I/O  
GND  
VCCA  
GND  
VCCR  
I/O  
GND  
VCCA  
GND  
VCCR  
I/O  
94  
NC  
I/O  
I/O  
95  
I/O  
I/O  
I/O  
96  
I/O  
I/O  
I/O  
97  
NC  
I/O  
I/O  
98  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
99  
NC  
I/O  
I/O  
100  
101  
102  
103  
104  
105  
106  
107  
108  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
NC  
GND  
I/O  
GND  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
Note: * Note that Pin 65 in the A54SX32—PQ208 is a no connect (NC).  
v3.2  
2-5  
54SX Family FPGAs  
208-Pin PQFP  
A54SX16,  
208-Pin PQFP  
A54SX16,  
A54SX08  
A54SX16P  
Function  
A54SX32  
Function  
A54SX08  
Function  
A54SX16P  
Function  
A54SX32  
Function  
Pin Number  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
Function  
VCCA  
GND  
I/O  
Pin Number  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
VCCA  
GND  
I/O  
VCCA  
GND  
I/O  
CLKB  
VCCR  
GND  
VCCA  
GND  
PRA, I/O  
I/O  
CLKB  
VCCR  
GND  
VCCA  
GND  
PRA, I/O  
I/O  
CLKB  
VCCR  
GND  
VCCA  
GND  
PRA, I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
NC  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
GND  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
VCCI  
NC  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TCK, I/O  
TCK, I/O  
TCK, I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CLKA  
CLKA  
CLKA  
Note: * Note that Pin 65 in the A54SX32—PQ208 is a no connect (NC).  
2-6  
v3.2  
54SX Family FPGAs  
144-Pin TQFP  
144  
1
144-Pin  
TQFP  
Figure 2-3 144-Pin TQFP (Top View)  
Note  
For Package Manufacturing and Environmental information, visit the Package Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
v3.2  
2-7  
54SX Family FPGAs  
144-Pin TQFP  
A54SX08 A54SX16P  
144-Pin TQFP  
A54SX32  
Function  
A54SX08  
Function  
A54SX16P  
Function  
A54SX32  
Function  
Pin Number  
Function  
GND  
TDI, I/O  
I/O  
Function  
GND  
TDI, I/O  
I/O  
Pin Number  
37  
1
GND  
TDI, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
2
38  
I/O  
3
39  
I/O  
I/O  
I/O  
4
I/O  
I/O  
I/O  
40  
I/O  
I/O  
I/O  
5
I/O  
I/O  
I/O  
41  
I/O  
I/O  
I/O  
6
I/O  
I/O  
I/O  
42  
I/O  
I/O  
I/O  
7
I/O  
I/O  
I/O  
43  
I/O  
I/O  
I/O  
8
I/O  
I/O  
I/O  
44  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
9
TMS  
VCCI  
GND  
I/O  
TMS  
VCCI  
GND  
I/O  
TMS  
VCCI  
GND  
I/O  
45  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
46  
I/O  
I/O  
I/O  
47  
I/O  
I/O  
I/O  
48  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
49  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
50  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
51  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
52  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
53  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
54  
PRB, I/O  
I/O  
PRB, I/O  
I/O  
PRB, I/O  
I/O  
VCCR  
VCCA  
I/O  
VCCR  
VCCA  
I/O  
VCCR  
VCCA  
I/O  
55  
56  
VCCA  
GND  
VCCR  
I/O  
VCCA  
GND  
VCCR  
I/O  
VCCA  
GND  
VCCR  
I/O  
57  
I/O  
I/O  
I/O  
58  
I/O  
I/O  
I/O  
59  
I/O  
I/O  
I/O  
60  
HCLK  
I/O  
HCLK  
I/O  
HCLK  
I/O  
I/O  
I/O  
I/O  
61  
I/O  
I/O  
I/O  
62  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
63  
I/O  
I/O  
I/O  
GND  
VCCI  
VCCA  
I/O  
GND  
VCCI  
VCCA  
I/O  
GND  
VCCI  
VCCA  
I/O  
64  
I/O  
I/O  
I/O  
65  
I/O  
I/O  
I/O  
66  
I/O  
I/O  
I/O  
67  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
68  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
69  
I/O  
I/O  
I/O  
70  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
71  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
GND  
GND  
GND  
72  
2-8  
v3.2  
54SX Family FPGAs  
144-Pin TQFP  
144-Pin TQFP  
A54SX08 A54SX16P  
A54SX08  
A54SX16P  
Function  
A54SX32  
Function  
A54SX32  
Function  
Pin Number  
73  
Function  
GND  
I/O  
Pin Number  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
Function  
GND  
I/O  
Function  
GND  
I/O  
GND  
I/O  
GND  
I/O  
GND  
I/O  
74  
75  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
76  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
77  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
78  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
79  
VCCA  
VCCI  
GND  
I/O  
VCCA  
VCCI  
GND  
I/O  
VCCA  
VCCI  
GND  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
80  
81  
I/O  
I/O  
I/O  
82  
I/O  
I/O  
I/O  
83  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
84  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
85  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
86  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
87  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
88  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
89  
VCCA  
VCCR  
I/O  
VCCA  
VCCR  
I/O  
VCCA  
VCCR  
I/O  
CLKA  
CLKB  
VCCR  
GND  
VCCA  
I/O  
CLKA  
CLKB  
VCCR  
GND  
VCCA  
I/O  
CLKA  
CLKB  
VCCR  
GND  
VCCA  
I/O  
90  
91  
92  
I/O  
I/O  
I/O  
93  
I/O  
I/O  
I/O  
94  
I/O  
I/O  
I/O  
95  
I/O  
I/O  
I/O  
PRA, I/O  
I/O  
PRA, I/O  
I/O  
PRA, I/O  
I/O  
96  
I/O  
I/O  
I/O  
97  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
98  
VCCA  
GND  
I/O  
VCCA  
GND  
I/O  
VCCA  
GND  
I/O  
I/O  
I/O  
I/O  
99  
I/O  
I/O  
I/O  
100  
101  
102  
103  
104  
105  
106  
107  
108  
I/O  
I/O  
I/O  
GND  
VCCI  
I/O  
GND  
VCCI  
I/O  
GND  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TCK, I/O  
TCK, I/O  
TCK, I/O  
v3.2  
2-9  
54SX Family FPGAs  
176-Pin TQFP  
176  
1
176-Pin  
TQFP  
Figure 2-4 176-Pin TQFP (Top View)  
Note  
For Package Manufacturing and Environmental information, visit the Package Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
2-10  
v3.2  
54SX Family FPGAs  
176-Pin TQFP  
A54SX16,  
176-Pin TQFP  
A54SX16,  
A54SX08  
Function  
A54SX16P  
Function  
A54SX32  
Function  
A54SX08  
Function  
A54SX16P  
Function  
A54SX32  
Function  
Pin Number  
Pin Number  
1
GND  
TDI, I/O  
NC  
GND  
TDI, I/O  
I/O  
GND  
TDI, I/O  
I/O  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
I/O  
I/O  
I/O  
I/O  
I/O  
2
I/O  
3
I/O  
I/O  
I/O  
4
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
5
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
6
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
7
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
8
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
9
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
TMS  
VCCI  
NC  
TMS  
VCCI  
I/O  
TMS  
VCCI  
I/O  
GND  
I/O  
GND  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
GND  
VCCA  
GND  
I/O  
GND  
VCCA  
GND  
I/O  
GND  
VCCA  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
PRB, I/O  
GND  
VCCA  
VCCR  
I/O  
PRB, I/O  
GND  
VCCA  
VCCR  
I/O  
PRB, I/O  
GND  
VCCA  
VCCR  
I/O  
I/O  
I/O  
I/O  
VCCI  
VCCA  
I/O  
VCCI  
VCCA  
I/O  
VCCI  
VCCA  
I/O  
v3.2  
2-11  
54SX Family FPGAs  
176-Pin TQFP  
A54SX16,  
176-Pin TQFP  
A54SX16,  
A54SX08  
A54SX16P  
Function  
A54SX32  
Function  
A54SX08  
Function  
A54SX16P  
Function  
A54SX32  
Function  
Pin Number  
69  
Function  
HCLK  
I/O  
Pin Number  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
HCLK  
I/O  
HCLK  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
70  
71  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
72  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
73  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
74  
I/O  
I/O  
I/O  
GND  
VCCA  
GND  
I/O  
GND  
VCCA  
GND  
I/O  
GND  
VCCA  
GND  
I/O  
75  
I/O  
I/O  
I/O  
76  
I/O  
I/O  
I/O  
77  
I/O  
I/O  
I/O  
78  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
79  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
80  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
81  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
82  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
83  
I/O  
I/O  
I/O  
84  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
85  
I/O  
I/O  
I/O  
I/O  
I/O  
86  
I/O  
I/O  
I/O  
NC  
NC  
VCCA  
GND  
VCCI  
I/O  
I/O  
I/O  
87  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
I/O  
I/O  
88  
VCCA  
GND  
VCCI  
I/O  
VCCA  
GND  
VCCI  
I/O  
89  
GND  
NC  
GND  
I/O  
GND  
I/O  
90  
91  
NC  
I/O  
I/O  
92  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
93  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
94  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
95  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
96  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
97  
I/O  
I/O  
I/O  
NC  
NC  
GND  
I/O  
I/O  
I/O  
98  
VCCA  
VCCI  
I/O  
VCCA  
VCCI  
I/O  
VCCA  
VCCI  
I/O  
I/O  
I/O  
99  
GND  
I/O  
GND  
I/O  
100  
101  
102  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
2-12  
v3.2  
54SX Family FPGAs  
176-Pin TQFP  
A54SX16,  
176-Pin TQFP  
A54SX16,  
A54SX08  
Function  
A54SX16P  
Function  
A54SX32  
Function  
A54SX08  
A54SX16P  
Function  
A54SX32  
Function  
Pin Number  
137  
Pin Number  
157  
Function  
PRA, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
PRA, I/O  
I/O  
PRA, I/O  
I/O  
138  
158  
139  
I/O  
I/O  
I/O  
159  
I/O  
I/O  
I/O  
140  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
160  
I/O  
I/O  
I/O  
141  
161  
I/O  
I/O  
I/O  
142  
I/O  
I/O  
I/O  
162  
I/O  
I/O  
I/O  
143  
I/O  
I/O  
I/O  
163  
I/O  
I/O  
I/O  
144  
I/O  
I/O  
I/O  
164  
I/O  
I/O  
I/O  
145  
I/O  
I/O  
I/O  
165  
I/O  
I/O  
I/O  
146  
I/O  
I/O  
I/O  
166  
I/O  
I/O  
I/O  
147  
I/O  
I/O  
I/O  
167  
I/O  
I/O  
I/O  
148  
I/O  
I/O  
I/O  
168  
NC  
I/O  
I/O  
149  
I/O  
I/O  
I/O  
169  
VCCI  
I/O  
VCCI  
I/O  
VCCI  
I/O  
150  
I/O  
I/O  
I/O  
170  
151  
I/O  
I/O  
I/O  
171  
NC  
I/O  
I/O  
152  
CLKA  
CLKB  
VCCR  
GND  
VCCA  
CLKA  
CLKB  
VCCR  
GND  
VCCA  
CLKA  
CLKB  
VCCR  
GND  
VCCA  
172  
NC  
I/O  
I/O  
153  
173  
NC  
I/O  
I/O  
154  
174  
I/O  
I/O  
I/O  
155  
175  
I/O  
I/O  
I/O  
156  
176  
TCK, I/O  
TCK, I/O  
TCK, I/O  
v3.2  
2-13  
54SX Family FPGAs  
100-Pin VQFP  
100  
1
100-Pin  
VQFP  
Figure 2-5 100-Pin VQFP (Top View)  
Note  
For Package Manufacturing and Environmental information, visit the Package Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
2-14  
v3.2  
54SX Family FPGAs  
100-Pin VQFP  
100-Pin VQFP  
100-Pin VQFP  
A54SX16,  
A54SX08 A54SX16P  
A54SX16,  
A54SX08 A54SX16P  
A54SX16,  
A54SX08 A54SX16P  
Pin  
Pin  
Pin  
Number  
Function  
GND  
TDI, I/O  
I/O  
Function  
GND  
TDI, I/O  
I/O  
Number  
Function  
VCCA  
GND  
VCCR  
I/O  
Function  
VCCA  
GND  
VCCR  
I/O  
Number  
Function  
GND  
I/O  
Function  
GND  
I/O  
1
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
2
3
I/O  
I/O  
4
I/O  
I/O  
I/O  
I/O  
5
I/O  
I/O  
HCLK  
I/O  
HCLK  
I/O  
I/O  
I/O  
6
I/O  
I/O  
I/O  
I/O  
7
TMS  
VCCI  
GND  
I/O  
TMS  
VCCI  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
8
I/O  
I/O  
I/O  
I/O  
9
I/O  
I/O  
I/O  
I/O  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
TDO, I/O  
I/O  
TDO, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CLKA  
CLKB  
VCCR  
VCCA  
GND  
PRA, I/O  
I/O  
CLKA  
CLKB  
VCCR  
VCCA  
GND  
PRA, I/O  
I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
VCCI  
I/O  
VCCA  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TCK, I/O  
TCK, I/O  
I/O  
I/O  
VCCA  
GND  
VCCA  
GND  
PRB, I/O  
PRB, I/O  
v3.2  
2-15  
54SX Family FPGAs  
313-Pin PBGA  
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25  
A
B
C
D
E
A
B
C
D
E
F
F
G
G
H
J
H
J
K
L
K
L
M
N
P
M
N
P
R
R
T
T
U
U
V
V
W
W
Y
Y
AA  
AA  
AB  
AC  
AB  
AC  
AD  
AE  
AD  
AE  
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25  
Figure 2-6 313-Pin PBGA (Top View)  
Note  
For Package Manufacturing and Environmental information, visit the Package Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
2-16  
v3.2  
54SX Family FPGAs  
313-Pin PBGA  
313-Pin PBGA  
313-Pin PBGA  
313-Pin PBGA  
Pin  
Number  
A54SX32  
Function  
Pin  
Number  
A54SX32  
Function  
Pin  
A54SX32  
Function  
Pin  
A54SX32  
Function  
Number  
B10  
B12  
B14  
B16  
B18  
B20  
B22  
B24  
C1  
Number  
E15  
E17  
E19  
E21  
E23  
E25  
F2  
A1  
GND  
NC  
I/O  
I/O  
I/O  
I/O  
VCCR  
I/O  
I/O  
I/O  
I/O  
NC  
GND  
I/O  
I/O  
NC  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
NC  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
NC  
I/O  
I/O  
I/O  
I/O  
AC5  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
A3  
AC7  
A5  
AC9  
I/O  
I/O  
I/O  
A7  
AC11  
AC13  
AC15  
AC17  
AC19  
AC21  
AC23  
AC25  
AD2  
I/O  
I/O  
I/O  
A9  
VCCR  
I/O  
I/O  
I/O  
A11  
I/O  
I/O  
A13  
I/O  
I/O  
I/O  
A15  
I/O  
I/O  
F4  
I/O  
A17  
I/O  
TDI, I/O  
I/O  
F6  
NC  
I/O  
A19  
I/O  
C3  
F8  
A21  
NC  
C5  
NC  
I/O  
F10  
F12  
F14  
F16  
F18  
F20  
F22  
F24  
G1  
NC  
I/O  
A23  
GND  
I/O  
C7  
A25  
AD4  
C9  
I/O  
I/O  
AA1  
AA3  
AA5  
AA7  
AA9  
AA11  
AA13  
AA15  
AA17  
AA19  
AA21  
AA23  
AA25  
AB2  
AD6  
VCCI  
I/O  
C11  
C13  
C15  
C17  
C19  
C21  
C23  
C25  
D2  
I/O  
NC  
I/O  
AD8  
VCCI  
I/O  
AD10  
AD12  
AD14  
AD16  
AD18  
AD20  
AD22  
AD24  
AE1  
I/O  
I/O  
PRB, I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
G3  
TMS  
I/O  
I/O  
NC  
I/O  
G5  
NC  
G7  
I/O  
I/O  
D4  
NC  
I/O  
G9  
VCCI  
I/O  
NC  
D6  
G11  
G13  
G15  
G17  
G19  
G21  
G23  
G25  
H2  
AE3  
I/O  
D8  
I/O  
CLKB  
I/O  
AE5  
I/O  
D10  
D12  
D14  
D16  
D18  
D20  
D22  
D24  
E1  
I/O  
AE7  
I/O  
I/O  
I/O  
AB4  
AE9  
I/O  
I/O  
I/O  
AB6  
AE11  
AE13  
AE15  
AE17  
AE19  
AE21  
AE23  
AE25  
B2  
I/O  
I/O  
I/O  
AB8  
VCCA  
I/O  
I/O  
I/O  
AB10  
AB12  
AB14  
AB16  
AB18  
AB20  
AB22  
AB24  
AC1  
AC3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
H4  
I/O  
I/O  
H6  
I/O  
TDO, I/O  
GND  
TCK, I/O  
I/O  
E3  
NC  
I/O  
H8  
I/O  
E5  
H10  
H12  
H14  
H16  
H18  
I/O  
E7  
I/O  
PRA, I/O  
I/O  
B4  
E9  
I/O  
B6  
I/O  
E11  
E13  
I/O  
I/O  
B8  
I/O  
VCCA  
NC  
v3.2  
2-17  
54SX Family FPGAs  
313-Pin PBGA  
313-Pin PBGA  
313-Pin PBGA  
313-Pin PBGA  
Pin  
Number  
A54SX32  
Function  
Pin  
A54SX32  
Function  
Pin  
Number  
A54SX32  
Function  
Pin  
A54SX32  
Function  
Number  
L25  
M2  
Number  
V10  
V12  
V14  
V16  
V18  
V20  
V22  
V24  
W1  
H20  
H22  
H24  
J1  
I/O  
I/O  
I/O  
R5  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
HCLK  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCA  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
VCCA  
VCCI  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
NC  
VCCI  
I/O  
R7  
M4  
I/O  
R9  
I/O  
M6  
I/O  
R11  
R13  
R15  
R17  
R19  
R21  
R23  
R25  
T2  
J3  
I/O  
M8  
I/O  
J5  
I/O  
M10  
M12  
M14  
M16  
M18  
M20  
M22  
M24  
N1  
I/O  
J7  
NC  
I/O  
GND  
GND  
VCCI  
I/O  
J9  
J11  
J13  
J15  
J17  
J19  
J21  
J23  
J25  
K2  
I/O  
CLKA  
I/O  
W3  
I/O  
W5  
I/O  
I/O  
W7  
I/O  
I/O  
T4  
W9  
GND  
I/O  
I/O  
T6  
W11  
W13  
W15  
W17  
W19  
W21  
W23  
W25  
Y2  
N3  
VCCA  
VCCR  
I/O  
T8  
I/O  
N5  
T10  
T12  
T14  
T16  
T18  
T20  
T22  
T24  
U1  
I/O  
N7  
K4  
I/O  
N9  
VCCI  
GND  
GND  
GND  
I/O  
K6  
I/O  
N11  
N13  
N15  
N17  
N19  
N21  
N23  
N25  
P2  
K8  
VCCI  
I/O  
K10  
K12  
K14  
K16  
K18  
K20  
K22  
K24  
L1  
I/O  
I/O  
I/O  
Y4  
I/O  
I/O  
Y6  
I/O  
VCCR  
VCCA  
I/O  
U3  
Y8  
VCCA  
I/O  
U5  
Y10  
Y12  
Y14  
Y16  
Y18  
Y20  
Y22  
Y24  
U7  
I/O  
P4  
I/O  
U9  
I/O  
P6  
I/O  
U11  
U13  
U15  
U17  
U19  
U21  
U23  
U25  
V2  
L3  
I/O  
P8  
I/O  
L5  
I/O  
P10  
P12  
P14  
P16  
P18  
P20  
P22  
P24  
R1  
I/O  
L7  
I/O  
GND  
GND  
I/O  
L9  
I/O  
L11  
L13  
L15  
L17  
L19  
L21  
L23  
I/O  
GND  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
V4  
I/O  
I/O  
V6  
I/O  
R3  
I/O  
V8  
2-18  
v3.2  
54SX Family FPGAs  
329-Pin PBGA  
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA  
AB  
AC  
Figure 2-7 329-Pin PBGA (Top View)  
Note  
For Package Manufacturing and Environmental information, visit the Package Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
v3.2  
2-19  
54SX Family FPGAs  
329-Pin PBGA  
329-Pin PBGA  
329-Pin PBGA  
329-Pin PBGA  
Pin  
Number  
A54SX32  
Pin  
A54SX32  
Function  
Pin  
A54SX32  
Function  
Pin  
A54SX32  
Function  
Function  
GND  
GND  
VCCI  
NC  
Number  
AA13  
AA14  
AA15  
AA16  
AA17  
AA18  
AA19  
AA20  
AA21  
AA22  
AA23  
AB1  
Number  
AC2  
AC3  
AC4  
AC5  
AC6  
AC7  
AC8  
AC9  
AC10  
AC11  
AC12  
AC13  
AC14  
AC15  
AC16  
AC17  
AC18  
AC19  
AC20  
AC21  
AC22  
AC23  
B1  
Number  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
C1  
A1  
A2  
I/O  
I/O  
VCCI  
NC  
I/O  
I/O  
A3  
I/O  
I/O  
I/O  
A4  
I/O  
I/O  
I/O  
A5  
I/O  
I/O  
I/O  
I/O  
A6  
I/O  
I/O  
I/O  
I/O  
A7  
VCCI  
NC  
I/O  
I/O  
I/O  
A8  
TDO, I/O  
VCCI  
I/O  
VCCI  
I/O  
I/O  
A9  
I/O  
GND  
VCCI  
NC  
TDI, I/O  
GND  
I/O  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
AA1  
AA2  
AA3  
AA4  
AA5  
AA6  
AA7  
AA8  
AA9  
AA10  
AA11  
AA12  
I/O  
I/O  
I/O  
VCCI  
I/O  
I/O  
I/O  
I/O  
C2  
CLKB  
I/O  
AB2  
GND  
I/O  
I/O  
C3  
AB3  
NC  
C4  
I/O  
AB4  
I/O  
I/O  
C5  
I/O  
I/O  
AB5  
I/O  
I/O  
C6  
I/O  
I/O  
AB6  
I/O  
I/O  
C7  
I/O  
I/O  
AB7  
I/O  
I/O  
C8  
I/O  
I/O  
AB8  
I/O  
I/O  
C9  
I/O  
I/O  
AB9  
I/O  
NC  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
C19  
C20  
C21  
C22  
C23  
D1  
I/O  
NC  
AB10  
AB11  
AB12  
AB13  
AB14  
AB15  
AB16  
AB17  
AB18  
AB19  
AB20  
AB21  
AB22  
AB23  
AC1  
I/O  
VCCI  
GND  
VCCI  
GND  
I/O  
I/O  
VCCI  
GND  
VCCI  
I/O  
PRB, I/O  
I/O  
I/O  
I/O  
HCLK  
I/O  
B2  
I/O  
B3  
I/O  
GND  
I/O  
I/O  
B4  
I/O  
I/O  
I/O  
B5  
I/O  
I/O  
I/O  
I/O  
B6  
I/O  
I/O  
I/O  
I/O  
B7  
I/O  
I/O  
I/O  
I/O  
B8  
I/O  
I/O  
I/O  
I/O  
B9  
I/O  
VCCI  
GND  
NC  
I/O  
I/O  
I/O  
B10  
I/O  
I/O  
GND  
I/O  
B11  
I/O  
I/O  
B12  
PRA, I/O  
CLKA  
I/O  
GND  
B13  
D2  
I/O  
2-20  
v3.2  
54SX Family FPGAs  
329-Pin PBGA  
329-Pin PBGA  
329-Pin PBGA  
329-Pin PBGA  
Pin  
Number  
A54SX32  
Function  
Pin  
A54SX32  
Function  
Pin  
A54SX32  
Function  
Pin  
A54SX32  
Function  
Number  
F22  
F23  
G1  
Number  
K20  
K21  
K22  
K23  
L1  
Number  
N11  
N12  
N13  
N14  
N20  
N21  
N22  
N23  
P1  
D3  
I/O  
TCK, I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
GND  
GND  
GND  
NC  
I/O  
D4  
D5  
I/O  
I/O  
D6  
I/O  
G2  
I/O  
I/O  
D7  
I/O  
G3  
I/O  
I/O  
D8  
I/O  
G4  
I/O  
L2  
I/O  
D9  
I/O  
G20  
G21  
G22  
G23  
H1  
I/O  
L3  
I/O  
I/O  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
D21  
D22  
D23  
E1  
I/O  
I/O  
L4  
VCCR  
GND  
GND  
GND  
GND  
GND  
VCCR  
I/O  
I/O  
VCCA  
VCCR  
I/O  
I/O  
L10  
L11  
L12  
L13  
L14  
L20  
L21  
L22  
L23  
M1  
I/O  
GND  
I/O  
P2  
I/O  
P3  
I/O  
I/O  
H2  
I/O  
P4  
I/O  
I/O  
H3  
I/O  
P10  
P11  
P12  
P13  
P14  
P20  
P21  
P22  
P23  
R1  
GND  
GND  
GND  
GND  
GND  
I/O  
I/O  
H4  
I/O  
I/O  
H20  
H21  
H22  
H23  
J1  
VCCA  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
M2  
I/O  
I/O  
I/O  
J2  
M3  
I/O  
I/O  
I/O  
J3  
I/O  
M4  
VCCA  
GND  
GND  
GND  
GND  
GND  
VCCA  
I/O  
I/O  
VCCI  
I/O  
J4  
I/O  
M10  
M11  
M12  
M13  
M14  
M20  
M21  
M22  
M23  
N1  
I/O  
E2  
J20  
J21  
J22  
J23  
K1  
I/O  
R2  
I/O  
E3  
I/O  
I/O  
R3  
I/O  
E4  
I/O  
I/O  
R4  
I/O  
E20  
E21  
E22  
E23  
F1  
I/O  
I/O  
R20  
R21  
R22  
R23  
T1  
I/O  
I/O  
I/O  
I/O  
I/O  
K2  
I/O  
I/O  
I/O  
K3  
I/O  
I/O  
I/O  
I/O  
K4  
I/O  
VCCI  
I/O  
I/O  
F2  
TMS  
I/O  
K10  
K11  
K12  
K13  
K14  
GND  
GND  
GND  
GND  
GND  
T2  
I/O  
F3  
N2  
I/O  
T3  
I/O  
F4  
I/O  
N3  
I/O  
T4  
I/O  
F20  
F21  
I/O  
N4  
I/O  
T20  
T21  
I/O  
I/O  
N10  
GND  
I/O  
v3.2  
2-21  
54SX Family FPGAs  
329-Pin PBGA  
329-Pin PBGA  
329-Pin PBGA  
329-Pin PBGA  
Pin  
Number  
A54SX32  
Function  
Pin  
Number  
A54SX32  
Function  
Pin  
A54SX32  
Function  
Pin  
Number  
A54SX32  
Function  
Number  
W23  
Y1  
T22  
T23  
U1  
I/O  
V4  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
NC  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Y12  
VCCA  
VCCR  
I/O  
I/O  
V20  
V21  
V22  
V23  
W1  
Y13  
I/O  
Y2  
Y14  
U2  
I/O  
Y3  
Y15  
I/O  
U3  
VCCA  
I/O  
Y4  
Y16  
I/O  
U4  
Y5  
Y17  
I/O  
U20  
U21  
U22  
U23  
V1  
I/O  
W2  
Y6  
Y18  
I/O  
VCCA  
I/O  
W3  
Y7  
Y19  
I/O  
W4  
Y8  
Y20  
GND  
I/O  
I/O  
W20  
W21  
W22  
Y9  
Y21  
VCCI  
I/O  
Y10  
Y11  
Y22  
I/O  
V2  
Y23  
I/O  
V3  
I/O  
2-22  
v3.2  
54SX Family FPGAs  
144-Pin FBGA  
4
1
2
3
5
6
7
8
10 11 12  
9
A
B
C
D
E
F
G
H
J
K
L
M
Figure 2-8 144-Pin FBGA (Top View)  
Note  
For Package Manufacturing and Environmental information, visit the Package Resource center at  
http://www.actel.com/products/rescenter/package/index.html.  
v3.2  
2-23  
54SX Family FPGAs  
144-Pin FBGA  
144-Pin FBGA  
144-Pin FBGA  
144-Pin FBGA  
Pin  
Number  
A54SX08  
Function  
Pin  
A54SX08  
Function  
Pin  
A54SX08  
Function  
Pin  
Number  
A54SX08  
Function  
Number  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
D10  
D11  
D12  
E1  
Number  
G1  
G2  
G3  
G4  
G5  
G6  
G7  
G8  
G9  
G10  
G11  
G12  
H1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
A12  
B1  
I/O  
I/O  
VCCI  
TDI, I/O  
I/O  
I/O  
GND  
I/O  
K1  
I/O  
I/O  
I/O  
K2  
I/O  
K3  
I/O  
I/O  
I/O  
K4  
I/O  
VCCA  
GND  
CLKA  
I/O  
I/O  
GND  
GND  
GND  
VCCI  
I/O  
K5  
I/O  
I/O  
K6  
I/O  
I/O  
K7  
GND  
I/O  
I/O  
K8  
I/O  
I/O  
K9  
I/O  
I/O  
I/O  
I/O  
K10  
K11  
K12  
L1  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
B2  
GND  
I/O  
E2  
I/O  
H2  
I/O  
L2  
B3  
E3  
I/O  
H3  
I/O  
L3  
I/O  
B4  
I/O  
E4  
I/O  
H4  
I/O  
L4  
I/O  
B5  
I/O  
E5  
TMS  
VCCI  
VCCI  
VCCI  
VCCA  
I/O  
H5  
VCCA  
VCCA  
VCCI  
VCCI  
VCCA  
I/O  
L5  
I/O  
B6  
I/O  
E6  
H6  
L6  
I/O  
B7  
CLKB  
I/O  
E7  
H7  
L7  
HCLK  
I/O  
B8  
E8  
H8  
L8  
B9  
I/O  
E9  
H9  
L9  
I/O  
B10  
B11  
B12  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
C10  
C11  
C12  
I/O  
E10  
E11  
E12  
F1  
H10  
H11  
H12  
J1  
L10  
L11  
L12  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
M8  
M9  
M10  
M11  
M12  
I/O  
GND  
I/O  
GND  
I/O  
I/O  
I/O  
VCCR  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
F2  
I/O  
J2  
I/O  
I/O  
TCK, I/O  
I/O  
F3  
VCCR  
I/O  
J3  
I/O  
I/O  
F4  
J4  
I/O  
I/O  
I/O  
F5  
GND  
GND  
GND  
VCCI  
I/O  
J5  
I/O  
I/O  
PRA, I/O  
I/O  
F6  
J6  
PRB, I/O  
I/O  
I/O  
F7  
J7  
VCCA  
I/O  
I/O  
F8  
J8  
I/O  
I/O  
F9  
J9  
I/O  
I/O  
I/O  
F10  
F11  
F12  
GND  
I/O  
J10  
J11  
J12  
I/O  
I/O  
I/O  
I/O  
TDO, I/O  
I/O  
I/O  
I/O  
VCCA  
2-24  
v3.2  
54SX Family FPGAs  
Datasheet Information  
List of Changes  
The following table lists critical changes that were made in the current version of the document.  
Previous Version Changes in Current Version (v3.2)  
Page  
1-ii  
v3.1  
The "Ordering Information" was updated to include RoHS information.  
The Product Plan was removed since all products have been released.  
(June 2003)  
N/A  
Information concerning the TRST pin in the "Probe Circuit Control Pins" section was removed.  
The "Dedicated Test Mode" section is new.  
1-6  
1-6  
The "Programming" section is new.  
1-7  
A note was added to the "Power-Up Sequencing" table.  
1-15  
A note was added to the "Power-Down Sequencing" table. The 3.3 V comments were updated for the 1-15  
following devices: A54SX08, A54SX16, A54SX32.  
U11 and U13 were added to the "313-Pin PBGA" table.  
Storage temperature in Table 1-3 was updated.  
Table 1-1 was updated.  
2-17  
1-7  
v3.0.1  
1-5  
Datasheet Categories  
In order to provide the latest information to designers, some datasheets are published before data has been fully  
characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet  
Supplement." The definitions of these categories are as follows:  
Product Brief  
The product brief is a summarized version of a datasheet (advanced or production) containing general product  
information. This brief gives an overview of specific device and family information.  
Advanced  
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed  
grades. This information can be used as estimates, but not for production.  
Unmarked (production)  
This datasheet version contains information that is considered to be final.  
Datasheet Supplement  
The datasheet supplement gives specific device information for a derivative family that differs from the general family  
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and  
for specifications that do not differ between the two families.  
International Traffic in Arms Regulations (ITAR) and Export  
Administration Regulations (EAR)  
The products described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR) or the  
Export Administration Regulations (EAR). They may require an approved export license prior to their export. An export  
can include a release or disclosure to a foreign national inside or outside the United States.  
v3.2  
3-1  
Actel and the Actel logo are registered trademarks of Actel Corporation.  
All other trademarks are the property of their owners.  
www.actel.com  
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Actel Europe Ltd.  
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Actel Hong Kong  
www.actel.com.cn  
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