v3.2
™
SX Family FPGAs
u
e
Leading Edge Performance
Features
•
•
•
•
320 MHz Internal Performance
3.7 ns Clock-to-Out (Pin-to-Pin)
0.1 ns Input Setup
•
•
•
•
•
•
•
•
66 MHz PCI
CPLD and FPGA Integration
Single-Chip Solution
100% Resource Utilization with 100% Pin Locking
3.3 V and 5.0 V Operation with 5.0 V Input Tolerance
Very Low Power Consumption
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Debug Capability
with Silicon Explorer II
0.25 ns Clock Skew
Specifications
•
•
•
•
12,000 to 48,000 System Gates
Up to 249 User-Programmable I/O Pins
Up to 1,080 Flip-Flops
•
•
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Secure Programming Technology Prevents Reverse
Engineering and Design Theft
0.35 µ CMOS
SX Product Profile
Device
A54SX08
A54SX16
A54SX16P
A54SX32
Capacity
Typical Gates
System Gates
8,000
12,000
16,000
24,000
16,000
24,000
32,000
48,000
Logic Modules
768
512
1,452
924
1,452
924
2,880
1,800
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
256
528
528
175
1,080
130
175
249
3
Yes
3
Yes
3
3
Yes
JTAG
Yes
PCI
–
–
Yes
–
Clock-to-Out
3.7 ns
0.8 ns
Std, –1, –2, –3
C, I, M
3.9 ns
0.5 ns
Std, –1, –2, –3
C, I, M
4.4 ns
0.5 ns
Std, –1, –2, –3
C, I, M
4.6 ns
0.1 ns
Std, –1, –2, –3
C, I, M
Input Setup (external)
Speed Grades
Temperature Grades
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
84
208
100
144, 176
–
144
–
208
100
176
–
–
208
100
144, 176
–
208
–
144, 176
313, 329
–
–
–
–
June 2006
i
© 2006 Actel Corporation
See the Actel website for the latest version of the datasheet.
ACTEL [ Actel Corporation ]
