Integrator Series FPGAs: 1200XL and 3200DX Families
A32100DX Timing Characteristics (continued)
(Worst-Case Commercial Conditions V
= 4.75 V, T = 70°C)
J
CC
3.3V ‘Std’
Speed
‘–3 Speed
‘–2 Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Timing
Synchronous SRAM Operations
tRC
Read Cycle Time
6.4
6.4
3.2
7.5
7.5
3.8
8.5
8.5
4.3
10.0
10.0
5.0
14.3
14.3
7.1
11.7
11.7
5.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
tRCKHL
tRCO
tADSU
tADH
Clock High/Low Time
Data Valid After Clock High/Low
Address/Data Set-Up Time
Address/Data Hold Time
Read Enable Set-Up
Read Enable Hold
3.2
3.8
4.3
5.0
7.1
5.9
1.5
0.0
0.6
3.2
2.6
0.0
2.6
0.0
1.8
0.0
0.7
3.8
3.0
0.0
3.1
0.0
2.0
0.0
0.8
4.3
3.4
0.0
3.5
0.0
2.4
0.0
0.9
5.0
4.0
0.0
4.1
0.0
3.4
0.0
1.3
7.1
5.7
0.0
5.8
0.0
2.8
0.0
1.0
5.9
4.7
0.0
4.8
0.0
tRENSU
tRENH
tWENSU
tWENH
tBENS
tBENH
Write Enable Set-Up
Write Enable Hold
Block Enable Set-Up
Block Enable Hold
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
Read Address Valid
7.7
9.0
10.2
12.0
17.2
14.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRDADV
tADSU
tADH
8.3
1.5
0.0
0.57
3.2
2.6
0.0
9.8
1.8
0.0
0.7
3.8
3.0
0.0
11.1
2.0
0.0
0.8
4.3
3.4
0.0
13.0
2.4
0.0
0.9
5.0
4.0
0.0
18.6
3.4
0.0
1.3
7.1
5.7
0.0
15.2
2.8
0.0
1.0
5.9
4.7
0.0
Address/Data Set-Up Time
Address/Data Hold Time
Read Enable Set-Up to Address Valid
Read Enable Hold
tRENSUA
tRENHA
tWENSU
tWENH
tDOH
Write Enable Set-Up
Write Enable Hold
Data Out Hold Time
1.1
1.35
1.5
1.8
2.6
2.1
Discontinued – v3.0
41
ACTEL [ Actel Corporation ]
