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A1280XL-FPGC 参数 Datasheet PDF下载

A1280XL-FPGC图片预览
型号: A1280XL-FPGC
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号A1280XL-FPGC的Datasheet PDF文件第28页浏览型号A1280XL-FPGC的Datasheet PDF文件第29页浏览型号A1280XL-FPGC的Datasheet PDF文件第30页浏览型号A1280XL-FPGC的Datasheet PDF文件第31页浏览型号A1280XL-FPGC的Datasheet PDF文件第33页浏览型号A1280XL-FPGC的Datasheet PDF文件第34页浏览型号A1280XL-FPGC的Datasheet PDF文件第35页浏览型号A1280XL-FPGC的Datasheet PDF文件第36页  
Integrator Series FPGAs: 1200XL and 3200DX Families  
A1240XL Timing Characteristics (continued)  
(Worst-Case Commercial Conditions V  
= 4.75 V, T = 70°C)  
J
CC  
‘–2’ Speed  
Min. Max.  
3.3V ‘Std’  
Speed  
‘–1’ Speed  
Min. Max.  
‘Std’ Speed  
‘–F’ Speed  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Units  
Input Module Propagation Delays  
t
t
t
t
Pad-to-Y High  
Pad-to-Y Low  
G-to-Y High  
G-to-Y Low  
1.1  
1.3  
2.0  
2.6  
1.2  
1.4  
2.3  
3.0  
1.4  
1.7  
2.7  
3.5  
2.0  
2.4  
3.9  
5.0  
1.7  
2.0  
3.2  
4.2  
ns  
ns  
ns  
ns  
INYH  
INYL  
INGH  
INGL  
1
Input Module Predicted Routing Delays  
t
t
t
t
t
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
2.9  
3.4  
3.8  
4.1  
5.6  
3.3  
3.8  
4.3  
4.7  
6.3  
3.9  
4.5  
5.1  
5.5  
7.4  
5.6  
6.4  
4.7  
5.4  
6.1  
6.6  
8.9  
ns  
ns  
ns  
ns  
ns  
IRD1  
IRD2  
IRD3  
IRD4  
IRD8  
7.3  
7.9  
10.6  
Global Clock Network  
FO = 32  
FO = 256  
5.1  
5.7  
5.8  
6.5  
6.8  
7.6  
9.7  
10.9  
8.2  
9.1  
ns  
ns  
t
t
t
t
t
t
t
t
f
Input Low to High  
Input High to Low  
CKH  
FO = 32  
FO = 256  
5.0  
5.7  
5.7  
6.5  
6.7  
7.6  
9.6  
10.9  
8.0  
9.1  
ns  
ns  
CKL  
FO = 32  
FO = 256  
2.7  
2.9  
3.1  
3.3  
3.6  
3.9  
5.1  
5.6  
4.3  
4.7  
ns  
ns  
Minimum Pulse Width High  
Minimum Pulse Width Low  
Maximum Skew  
PWH  
PWL  
CKSW  
SUEXT  
HEXT  
P
FO = 32  
FO = 256  
2.7  
2.9  
3.1  
3.3  
3.6  
3.9  
5.1  
5.6  
4.3  
4.7  
ns  
ns  
FO = 32  
FO = 256  
0.8  
0.8  
0.9  
0.9  
1.0  
1.0  
1.4  
1.4  
1.2  
1.2  
ns  
ns  
FO = 32  
FO = 256  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
ns  
ns  
Input Latch External Set-Up  
Input Latch External Hold  
Minimum Period  
FO = 32  
FO = 256  
2.6  
3.2  
2.9  
3.7  
3.4  
4.3  
4.9  
6.1  
4.1  
5.2  
ns  
ns  
FO = 32  
FO = 256  
5.6  
6.0  
6.3  
6.8  
7.4  
8.0  
10.6  
11.4  
8.9  
9.6  
ns  
ns  
FO = 32  
FO = 256  
215  
195  
190  
170  
160  
144  
110  
100  
105  
95  
MHz  
MHz  
Maximum Frequency  
MAX  
Note:  
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual performance.  
32  
Discontinued – v3.0  
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