Integrator Series FPGAs: 1200XL and 3200DX Families
Package Pin Assignments (continued)
132-Pin CPGA (Top View)
1
2
3
4
5
6
7
8
9
10 11 12 13
A
B
C
D
E
F
A
B
C
D
E
F
132-Pin
CPGA
G
H
J
G
H
J
K
L
K
L
M
N
M
N
1
2
3
4
5
6
7
8
9
10 11 12 13
Orientation Pin
Signal
Pad Number
Location
PRA or I/O
PRB or I/O
MODE
113
121
2
B8
C6
A1
SDI or I/O
DCLK or I/O
CLKA or I/O
CLKB or I/O
GND
101
132
115
119
B12
C3
B7
B6
9, 10, 26, 27, 41, 58, 59, 73, 74, 92, 93, 107, 108, 125, 126
18, 19, 49, 50, 83, 84, 116, 117
E3, F4, J2, J3, L5, L9, M9, K12, J11, H13, E12, E11, C9, B9, B5, C5
G3, G2, G4, L7, K7, G10, G11, G12, G13, D7, C7
V
CC
Notes:
1. Unused I/O pins are designated as outputs by ALS and are driven LOW.
2. All unassigned pins are available for use as I/Os.
3. MODE = GND, except during device programming or debugging.
Discontinued – v3.0
77
ACTEL [ Actel Corporation ]
