Integrator Series FPGAs: 1200XL and 3200DX Families
Predictable Performance:
Tight Delay Distributions
are not determined until after placement and routing of the
user’s design is complete. Delay values may then be
determined by using the Designer Series utility or
Propagation delay between logic modules depends on the
resistive and capacitive loading of the routing tracks, the
interconnect elements, and the module inputs being driven.
Propagation delay increases as the length of routing tracks,
the number of interconnect elements, or the number of
inputs increase.
performing simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays in this data sheet apply to typical nets,
which are used for initial design performance evaluation.
The abundant routing resources in the Integrator Series
architecture allows for deterministic timing. Using
DirectTime, a timing-driven place and route tool in Actel’s
Designer Series development software, the designer may
specify timing-critical nets and system clock frequency.
Using these timing specifications, the place and route
software optimize the design layout to meet the user’s
specifications.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout (number of
loads) driven by a module. Higher fanout usually requires
some paths to have longer routing tracks.
The Integrator Series delivers a very tight fanout delay
distribution. This tight distribution is achieved in two ways:
by decreasing the delay of the interconnect elements and by
decreasing the number of interconnect elements per path.
Long Tracks
Some nets in the design use long tracks, which are special
routing resources that span multiple rows, columns, or
modules. Long tracks employ three and sometimes four
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 3 ns to 6 ns delay, which is represented
statistically in higher fanout (FO=8) routing delays in the
data sheet specifications section.
Actel’s patented PLICE antifuse offers
a very low
resistive/capacitive interconnect. The antifuses, fabricated
in 0.6 micron lithography, offer nominal levels of 100 ohms
resistance and 7.0 femtofarad (fF) capacitance per antifuse.
The Integrator Series fanout distribution is also tight due to
the low number of antifuses required for each interconnect
path. The proprietary architecture limits the number of
antifuses per path to a maximum of four, with 90% of
interconnects using two antifuses.
Timing Characteristics
Timing Derating
A timing derating factor of 0.45 is used to reflect best-case
processing. Note that this factor is relative to the “standard
speed” timing parameters, and must be multiplied by the
appropriate voltage and temperature derating factors for a
given application.
Timing characteristics for devices fall into three categories:
family-dependent, device-dependent, and design-dependent.
The input and output buffer characteristics are common to
all Integrator Series members. Internal routing delays are
device-dependent. Design dependency means actual delays
Timing Derating Factor (Temperature and Voltage)
Industrial
Military
Min.
Max.
Min.
Max.
(Commercial Specification) x
0.69
1.11
0.67
1.23
Timing Derating Factor for Designs at Typical Temperature (T = 25°C)
J
and Voltage (5.0V)
(Maximum Specification, Worst-Case Condition) x
0.85
Note: This derating factor applies to all routing and propagation
delays.
26
Discontinued – v3.0
ACTEL [ Actel Corporation ]
