欢迎访问ic37.com |
会员登录 免费注册
发布采购

A1280DX-CQB 参数 Datasheet PDF下载

A1280DX-CQB图片预览
型号: A1280DX-CQB
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号A1280DX-CQB的Datasheet PDF文件第10页浏览型号A1280DX-CQB的Datasheet PDF文件第11页浏览型号A1280DX-CQB的Datasheet PDF文件第12页浏览型号A1280DX-CQB的Datasheet PDF文件第13页浏览型号A1280DX-CQB的Datasheet PDF文件第15页浏览型号A1280DX-CQB的Datasheet PDF文件第16页浏览型号A1280DX-CQB的Datasheet PDF文件第17页浏览型号A1280DX-CQB的Datasheet PDF文件第18页  
Integrator Series FPGAs: 1200XL and 3200DX Families  
Package Thermal Characteristics  
Maximum junction temperature is 150°C.  
The device junction to case thermal characteristic is θjc,  
and the junction to ambient air characteristic is θja. The  
thermal characteristics for θja are shown with two different  
air flow rates.  
A sample calculation of the absolute maximum power  
dissipation allowed for a PQFP 160-pin package with still air  
at commercial temperature is as follows:  
Max. junction temp. (°C) – Max. commercial temp.  
150°C – 70°C  
---------------------------------------------------------------------------------------------------------------------------- = --------------------------------- = 2 . 4 W  
θja (°C/W)  
34°C/W  
θ
Maximum Power Dissipation  
ja  
Pin Count  
Package Type  
Still Air  
300 ft/min  
Still Air  
300 ft/min  
Plastic Quad Flat Pack  
Plastic Quad Flat Pack  
Plastic Quad Flat Pack  
Plastic Quad Flat Pack  
Plastic Leaded Chip Carrier  
Thin Quad Flat Pack  
100  
144  
160  
208  
84  
42°C/W  
36°C/W  
34°C/W  
25°C/W  
37°C/W  
32°C/W  
16.8°C/W  
16.1°C/W  
43°C/W  
33°C/W  
29°C/W  
27°C/W  
16.2°C/W  
28°C/W  
25°C/W  
11.4°C/W  
10.6°C/W  
35°C/W  
1.9 W  
2.2 W  
2.4 W  
3.2 W  
2.2 W  
2.5 W  
4.8 W  
5.0 W  
1.9 W  
2.4 W  
2.8 W  
3.0 W  
4.9 W  
2.9 W  
3.2 W  
7.0 W  
7.5 W  
2.3 W  
176  
208  
240  
100  
Power Quad Flat Pack  
Power Quad Flat Pack  
Very Thin Quad Flat Pack  
Power Dissipation  
The power dissipation due to standby current is typically a  
small component of the overall power. Standby power is  
calculated below for commercial worst case conditions.  
General Power Equation  
P = [ICCstandby + ICCactive] * VCC + IOL* VOL* N  
+ IOH * (VCC – VOH) * M  
ICC  
VCC  
Power  
2 mA  
5.25 V  
10.5 mW  
where:  
The static power dissipation by TTL loads depends on the  
number of outputs driving HIGH or LOW and the DC load  
current. Again, this number is typically small. For instance,  
a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW with  
all outputs driving LOW and 140 mW with all outputs driving  
HIGH. The actual dissipation will average somewhere in  
between as I/Os switch states with time.  
ICCstandby is the current flowing when no inputs or  
outputs are changing.  
ICCactive is the current flowing due to CMOS switching.  
IOL, IOH are TTL sink/source currents.  
VOL, VOH are TTL level output voltages.  
N equals the number of outputs driving TTL loads to VOL  
.
Active Power Component  
M equals the number of outputs driving TTL loads to VOH  
.
Power dissipation in CMOS devices is usually dominated by  
the active (dynamic) power dissipation. This component is  
frequency-dependent, a function of the logic and the  
external I/O. Active power dissipation results from charging  
internal chip capacitances of the interconnect,  
unprogrammed antifuses, module inputs, and module  
outputs, plus external capacitance due to PC board traces  
and load device inputs. An additional component of the  
active power dissipation is the totem pole current in the  
CMOS transistor pairs. The net effect can be associated with  
an equivalent capacitance that can be combined with  
frequency and voltage to represent active power dissipation.  
An accurate determination of N and M is problematic  
because their values depend on the family type, design  
details, and on the system I/O. The power can be divided  
into two components: static and active.  
Static Power Component  
Actel FPGAs have small static power components that  
result in lower power dissipation than PALs or PLDs. By  
integrating multiple PALs/PLDs into one FPGA, an even  
greater reduction in board-level power dissipation can  
be achieved.  
14  
Discontinued – v3.0  
 复制成功!