ACT™ 2 Family FPGAs
A1225A Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
Logic Module Propagation Delays1
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
tPD1
tCO
tGO
tRS
Single Module
3.8
3.8
3.8
3.8
4.3
4.3
4.3
4.3
5.0
5.0
5.0
5.0
ns
ns
ns
ns
Sequential Clk to Q
Latch G to Q
Flip-Flop (Latch) Reset to Q
Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.1
1.7
2.3
2.8
4.4
1.2
1.9
2.6
3.1
4.9
1.4
2.2
3.0
3.7
5.8
ns
ns
ns
ns
ns
Sequential Timing Characteristics3,4
tSUD
Flip-Flop (Latch) Data Input
Setup
0.4
0.4
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
0.0
0.8
0.0
0.0
0.9
0.0
0.0
1.0
0.0
ns
ns
ns
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.5
4.5
5.0
5.0
6.0
6.0
ns
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
9.4
0.0
0.4
0.0
0.4
11.0
0.0
0.4
0.0
0.4
13.0
0.0
0.5
0.0
0.5
ns
ns
ns
ns
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Flip-Flop (Latch) Clock
Frequency
105.0
90.0
75.0
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
12
v4.0
ACTEL [ Actel Corporation ]
