ACT™ 2 Family FPGAs
A1225A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Unit
s
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
2.9
2.6
5.0
4.7
3.3
3.0
5.7
5.4
3.8
3.5
6.6
6.3
ns
ns
ns
ns
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
4.1
4.6
5.3
5.7
7.4
4.6
5.2
6.0
6.4
8.3
5.4
6.1
7.1
7.6
9.8
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input Low to High
tCKL
FO = 32
FO = 256
10.2
11.8
11.0
13.0
12.8
15.7
ns
ns
FO = 32
FO = 256
10.2
12.0
11.0
13.2
12.8
15.9
Input High to Low
Minimum Pulse Width
High
FO = 32
FO = 256
3.4
3.8
4.1
4.5
4.5
5.0
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
ns
Minimum Pulse Width
Low
FO = 32
FO = 256
3.4
3.8
4.1
4.5
4.5
5.0
ns
FO = 32
FO = 256
0.7
3.5
0.7
3.5
0.7
3.5
Maximum Skew
ns
Input Latch External
Setup
FO = 32
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
ns
Input Latch External
Hold
FO = 32
FO = 256
7.0
11.2
7.0
11.2
7.0
11.2
ns
FO = 32
FO = 256
7.7
8.1
8.3
8.8
9.1
10.0
Minimum Period
ns
FO = 32
FO = 256
130.0
125.0
120.0
115.0
110.0
100.0
fMAX
Maximum Frequency
MHz
Note:
1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns.
Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to
determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device
prior to shipment.
v4.0
13
ACTEL [ Actel Corporation ]
