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A1280A-PL84M 参数 Datasheet PDF下载

A1280A-PL84M图片预览
型号: A1280A-PL84M
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 1232 CLBs, 8000 Gates, CMOS, PQCC84, PLASTIC, LCC-84]
分类和应用: 可编程逻辑
文件页数/大小: 38 页 / 652 K
品牌: ACTEL [ Actel Corporation ]
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ACT2 Family FPGAs  
and load device inputs. An additional component of the  
active power dissipation is the totem-pole current in CMOS  
transistor pairs. The net effect can be associated with an  
equivalent capacitance that can be combined with  
frequency and voltage to represent active power dissipation.  
r2  
= Fixed capacitance due to second routed array  
clock  
CEQM = Equivalent capacitance of logic modules in pF  
CEQI = Equivalent capacitance of input buffers in pF  
CEQO = Equivalent capacitance of output buffers in pF  
Equivalent Capacitance  
CEQCR = Equivalent capacitance of routed array clock in  
pF  
The power dissipated by a CMOS circuit can be expressed by  
the Equation 1.  
Power (µW) = CEQ * VCC2 * F  
(1)  
CL  
fm  
fn  
= Output lead capacitance in pF  
Where:  
CEQ is the equivalent capacitance expressed in pF.  
CC is the power supply in volts.  
= Average logic module switching rate in MHz  
= Average input buffer switching rate in MHz  
= Average output buffer switching rate in MHz  
= Average first routed array clock rate in MHz  
= Average second routed array clock rate in MHz  
V
fp  
F is the switching frequency in MHz.  
fq1  
fq2  
Equivalent capacitance is calculated by measuring ICC  
active at a specified frequency and voltage for each circuit  
component of interest. Measurements have been made over  
a range of frequencies at a fixed value of VCC. Equivalent  
capacitance is frequency independent so that the results  
may be used over a wide range of operating conditions.  
Equivalent capacitance values are shown below.  
Fixed Capacitance Values for Actel FPGAs  
(pF)  
r1  
r2  
Device Type  
routed_Clk1  
routed_Clk2  
A1225A  
A1240A  
A1280A  
106  
134  
168  
106.0  
134.2  
167.8  
CEQ Values for Actel FPGAs  
Determining Average Switching Frequency  
To determine the switching frequency for a design, you must  
have a detailed understanding of the data input values to  
the circuit. The following guidelines are meant to represent  
worst-case scenarios so that they can be generally used to  
predict the upper limits of power dissipation. These  
guidelines are as follows:  
Modules (CEQM  
Input Buffers (CEQI  
Output Buffers (CEQO  
Routed Array Clock Buffer Loads (CEQCR  
)
5.8  
12.9  
23.8  
3.9  
)
)
)
To calculate the active power dissipated from the complete  
design, the switching frequency of each part of the logic  
must be known. Equation 2 shows a piece-wise linear  
summation over all components.  
Power = VCC2 * [(m * CEQM* fm)modules +(n * CEQI* fn)inputs  
+ (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR  
fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR  
fq2)routed_Clk2  
Logic Modules (m)  
80% of modules  
# inputs/4  
Inputs switching (n)  
Outputs switching (p)  
First routed array clock loads (q1)  
# outputs/4  
*
40%of  
*
sequential  
modules  
+ (r2 * fq2)routed_Clk2  
]
(2)  
Second routed array clock loads (q2)  
40%of  
Where:  
sequential  
modules  
m
n
= Number of logic modules switching at fm  
= Number of input buffers switching at fn  
= Number of output buffers switching at fp  
Load capacitance (CL)  
35 pF  
p
Average logic module switching rate (fm) F/10  
q1  
= Number of clock loads on the first routed array  
clock  
Average input switching rate (fn)  
Average output switching rate (fp)  
Average first routed array clock rate (fq1)  
F/5  
F/10  
F
q2  
r1  
= Number of clock loads on the second routed  
array clock  
Average second routed array clock rate F/2  
(fq2)  
= Fixed capacitance due to first routed array  
clock  
6
v4.0  
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