ACT™ 2 Family FPGAs
A1280A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Min.
Max.
Min.
Max.
Min.
Max.
Units
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
2.9
2.7
5.0
4.8
3.3
3.0
5.7
5.4
3.8
3.5
6.6
6.3
ns
ns
ns
ns
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
4.6
5.2
5.6
6.5
9.4
5.1
5.9
6.0
6.9
ns
ns
ns
ns
ns
6.3
7.4
7.3
8.6
10.5
12.4
Global Clock Network
tCKH Input Low to High
tCKL
FO = 32
FO = 384
10.2
13.1
11.0
14.6
12.8
17.2
ns
ns
FO = 32
FO = 384
10.2
13.3
11.0
14.9
12.8
17.5
Input High to Low
Minimum Pulse Width
High
FO = 32
FO = 384
5.0
5.8
5.5
6.4
6.6
7.6
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
ns
FO = 32
FO = 384
5.0
5.8
5.5
6.4
6.6
7.6
Minimum Pulse Width Low
Maximum Skew
ns
FO = 32
FO = 384
0.5
2.5
0.5
2.5
0.5
2.5
ns
FO = 32
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
Input Latch External Setup
Input Latch External Hold
Minimum Period
ns
FO = 32
FO = 384
7.0
11.2
7.0
11.2
7.0
11.2
ns
FO = 32
FO = 384
9.6
10.6
11.2
12.6
13.3
15.3
ns
FO = 32
FO = 384
105.0
95.0
90.0
80.0
75.0
65.0
fMAX
Maximum Frequency
MHz
Note:
These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing
delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual
worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
v4.0
19
ACTEL [ Actel Corporation ]
