HiRel FPGAs
A1240A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
Min. Max.
‘Std’ Speed
Min. Max.
Parameter
Description
Units
TTL Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
11.0
13.9
12.3
16.1
9.8
13.0
ns
ns
tDHL
16.4
14.4
19.0
11.5
13.6
14.6
18.2
0.11
0.20
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
ns
ns
11.5
12.4
15.5
0.09
0.17
ns
ns
tGHL
G to Pad Low
ns
dTLH
dTHL
Delta Low to High
Delta High to Low
ns/pF
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
14.0
11.7
12.3
16.1
9.8
16.5
13.7
14.4
19.0
11.5
13.6
14.6
18.2
0.20
0.15
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
ns
ns
11.5
12.4
15.5
0.17
0.12
ns
ns
tGHL
G to Pad Low
ns
dTLH
dTHL
Notes:
Delta Low to High
Delta High to Low
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
29
ACTEL [ Actel Corporation ]
