HiRel FPGAs
3200DX Timing Model (Logic Functions using Quadrant Clocks)*
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
I/O Module
tINPY = 1.9 ns
t
IRD1 = 2.2 ns
Combinatorial
Module
tDLH = 6.3 ns
tRD1 = 1.3 ns
tRD2 = 1.9 ns
tRD4 = 3.3 ns
D
G
Q
tPD = 3.1 ns
Decode
Module
tINH = 0.0 ns
INSU = 0.7 ns
tRDD = 0.5 ns
t
t
INGO = 4.0 ns
tPDD = 3.3 ns
I/O Module
tDLH = 6.3 ns
Sequential
Logic Module
tRD1 = 1.3 ns
Combin-
D
D
G
Q
Q
atorial
Logic
included
in tSUD
tENHZ = 11.5 ns
tLH = 0.0 ns
tLSU = 0.4 ns
tGHL= 12.4 ns
tCO = 3.1 ns
t
SU = 0.5 ns
tHD = 0.0 ns
QUADRANT
CLOCKS
t
CKH = 12 ns**
FMAX = 100 MHz
* Values shown for A32100DX–1 at worst-case military conditions.
** Load dependent.
15
ACTEL [ Actel Corporation ]
