Integrator Series FPGAs: 1200XL and 3200DX Families
Package Pin Assignments (continued)
176-Pin CPGA (Top View)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
176-Pin
CPGA
K
L
K
L
M
N
P
R
M
N
P
R
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Signal
Pad Number
Location
PRA or I/O
PRB or I/O
MODE
152
160
2
C9
D7
C3
B14
B3
SDI or I/O
DCLK or I/O
CLKA or I/O
CLKB or I/O
GND
135
175
154
158
A9
B8
1, 8, 18, 23, 33, 38, 45, 57, 67, 77, 89
101, 106, 111, 121, 126, 133, 145, 156, 165
D4, E4, G4, H4, K4, L4, M4, M6, M8, M10, M12
K12, J12, J13, H12, F12, E12, D12, D10, C8, D6
V
CC
13, 24, 28, 52, 68, 82, 112, 116, 140, 155, 170
F4, H2, H3, J4, M5, N8, M11, J14, H13, H14, G12, D11, D8, D5
Notes:
1. Unused I/O pins are designated as outputs by ALS and are driven LOW.
2. All unassigned pins are available for use as I/Os.
3. MODE = GND, except during device programming or debugging.
78
Discontinued – v3.0
ACTEL [ Actel Corporation ]
