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A1240DX-1PLB 参数 Datasheet PDF下载

A1240DX-1PLB图片预览
型号: A1240DX-1PLB
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
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Integrator Series FPGAs: 1200XL and 3200DX Families  
1200XL Timing Model*  
Input Delays  
Internal Delays  
Predicted  
Routing  
Delays  
Output Delays  
I/O Module  
Combinatorial  
Logic Module  
I/O Module  
t
INYL = 1.3 ns  
tIRD2 = 3.2 ns†  
t
DLH = 3.8 ns  
tRD1 = 0.8 ns  
tRD2 = 1.3 ns  
tRD4 = 2.0 ns  
D
Q
t
PD = 2.6 ns  
t
RD8 = 3.2 ns  
I/O Module  
tDLH = 3.8 ns  
G
Sequential  
Logic Module  
tINH = 0.0 ns  
tINSU = 0.3 ns  
tINGL = 2.6 ns  
Combin-  
atorial  
D
D
G
Q
Q
Logic  
included  
in tSUD  
tRD1 = 0.8 ns  
tENHZ = 5.4 ns  
tOUTH = 0.0 ns  
tOUTSU = 0.3 ns  
t
CO = 2.6 ns  
tSUD = 0.4 ns  
HD = 0.0 ns  
Array  
Clocks  
t
GLH = 4.2 ns  
t
tCKH = 5.7 ns  
FO = 256  
FMAX = 225 MHz  
tLCO = 10.7 ns (64 loads, pad-pad)  
Notes:  
1. *Values shown for A1225XL-2 at worst-case commercial conditions.†  
2. Input Module Predicted Routing Delay  
16  
Discontinued – v3.0  
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