A C T
™
2 F a m il y F P GA s
and load device inputs. An additional component of the
active power dissipation is the totem-pole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with
frequency and voltage to represent active power dissipation.
E quiv al ent C apac it ance
r
2
C
EQM
C
EQI
C
EQO
= Fixed capacitance due to second routed array
clock
= Equivalent capacitance of logic modules in pF
= Equivalent capacitance of input buffers in pF
= Equivalent capacitance of output buffers in pF
The power dissipated by a CMOS circuit can be expressed by
the Equation 1.
Power (
µ
W) = C
EQ
* V
CC2
* F
Where:
C
EQ
is the equivalent capacitance expressed in pF.
V
CC
is the power supply in volts.
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring ICC
active at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over
a range of frequencies at a fixed value of VCC. Equivalent
capacitance is frequency independent so that the results
may be used over a wide range of operating conditions.
Equivalent capacitance values are shown below.
C
E Q
Va lues f or Ac tel F PG A s
C
EQCR
= Equivalent capacitance of routed array clock in
pF
C
L
f
m
f
n
f
p
f
q1
f
q2
= Output lead capacitance in pF
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in MHz
(1)
Fi xed Ca paci ta nce Val ues fo r Act el FP GA s
(pF )
Device Type
A1225A
A1240A
A1280A
r1
routed_Clk1
106
134
168
r2
routed_Clk2
106.0
134.2
167.8
Modules (C
EQM
)
Input Buffers (C
EQI
)
Output Buffers (C
EQO
)
Routed Array Clock Buffer Loads (C
EQCR
)
5.8
12.9
23.8
3.9
D et erm i nin g A ve ra ge S wi t chi ng F re quenc y
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic
must be known. Equation 2 shows a piece-wise linear
summation over all components.
Power = V
CC2
* [(m * C
EQM
* f
m
)
modules
+(n * C
EQI
* f
n
)
inputs
+ (p * (C
EQO
+ C
L
) * f
p
)
outputs
+ 0.5 * (q
1
* C
EQCR
*
f
q1
)
routed_Clk1
+ (r
1
* f
q1
)
routed_Clk1
+ 0.5 * (q
2
* C
EQCR
*
f
q2
)
routed_Clk2
(2)
+ (r
2
* f
q2
)
routed_Clk2
]
Where:
m
n
p
q1
q2
r
1
= Number of logic modules switching at fm
= Number of input buffers switching at fn
= Number of output buffers switching at fp
= Number of clock loads on the first routed array
clock
= Number of clock loads on the second routed
array clock
= Fixed capacitance due to first routed array
clock
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to
the circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
Logic Modules (m)
Inputs switching (n)
Outputs switching (p)
First routed array clock loads (q
1
)
80% of modules
# inputs/4
# outputs/4
40%of
sequential
modules
40%of
sequential
modules
35 pF
F/10
F/5
F/10
F
Second routed array clock loads (q
2
)
Load capacitance (C
L
)
Average logic module switching rate (f
m
)
Average input switching rate (f
n
)
Average output switching rate (f
p
)
Average first routed array clock rate (f
q1
)
Average second routed array clock rate F/2
(f
q2
)
6
v4.0
ACTEL [ Actel Corporation ]
