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A1240A-1PL176C 参数 Datasheet PDF下载

A1240A-1PL176C图片预览
型号: A1240A-1PL176C
PDF下载: 下载PDF文件 查看货源
内容描述: ACT2系列FPGA [ACT2 Family FPGAs]
分类和应用:
文件页数/大小: 38 页 / 610 K
品牌: ACTEL [ Actel Corporation ]
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ACT2 Family FPGAs  
A1240A Timing Characteristics  
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)  
Logic Module Propagation Delays1  
‘–2Speed  
‘–1Speed  
StdSpeed  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Units  
tPD1  
tCO  
tGO  
tRS  
Single Module  
3.8  
3.8  
3.8  
3.8  
4.3  
4.3  
4.3  
4.3  
5.0  
5.0  
5.0  
5.0  
ns  
ns  
ns  
ns  
Sequential Clk to Q  
Latch G to Q  
Flip-Flop (Latch) Reset to Q  
Predicted Routing Delays2  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
1.4  
1.7  
2.3  
3.1  
4.7  
1.5  
2.0  
2.6  
3.5  
5.4  
1.8  
2.3  
3.0  
4.1  
6.3  
ns  
ns  
ns  
ns  
ns  
Sequential Timing Characteristics3, 4  
Flip-Flop (Latch) Data Input  
Setup  
tSUD  
0.4  
0.0  
0.4  
0.0  
0.5  
0.0  
ns  
ns  
Flip-Flop (Latch) Data Input  
Hold  
tHD  
tSUENA  
tHENA  
Flip-Flop (Latch) Enable Setup  
Flip-Flop (Latch) Enable Hold  
0.8  
0.0  
0.9  
0.0  
1.0  
0.0  
ns  
ns  
Flip-Flop (Latch) Clock Active  
Pulse Width  
tWCLKA  
tWASYN  
4.5  
4.5  
6.0  
6.0  
6.5  
6.5  
ns  
ns  
Flip-Flop (Latch)  
Asynchronous Pulse Width  
tA  
Flip-Flop Clock Input Period  
Input Buffer Latch Hold  
Input Buffer Latch Setup  
Output Buffer Latch Hold  
Output Buffer Latch Setup  
9.8  
0.0  
0.4  
0.0  
0.4  
12.0  
0.0  
0.4  
0.0  
0.4  
15.0  
0.0  
0.5  
0.0  
0.5  
ns  
ns  
ns  
ns  
ns  
tINH  
tINSU  
tOUTH  
tOUTSU  
Flip-Flop (Latch) Clock  
Frequency  
fMAX  
100.0  
80.0  
66.0  
MHz  
Notes:  
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is  
based on actual routing delay measurements performed on the device prior to shipment.  
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained  
from the DirectTime Analyzer utility.  
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold  
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input  
subtracts (adds) to the internal setup (hold) time.  
v4.0  
15  
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