can be combined with frequency and voltage to represent
active power dissipation.
where:
m
n
= Number of logic modules switching at fm
= Number of input buffers switching at fn
= Number of output buffers switching at fp
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
Equation 1:
p
q1
= Number of clock loads on the first routed
array clock (all families)
Power (uW) = CEQ * VCC2 * F
(1)
where:
CEQ
VCC
F
q2
= Number of clock loads on the second routed
array clock (ACT 2, 1200XL, 3200DX, ACT 3
only)
= Equivalent capacitance in pF
= Power supply in volts (V)
= Switching frequency in MHz
r1
r2
s1
s2
= Fixed capacitance due to first routed array
clock (all families)
Equivalent capacitance is calculated by measuring ICCactive
at a specified frequency and voltage for each circuit
component of interest. Measurements are made over a range
of frequencies at a fixed value of VCC. Equivalent capacitance
is frequency independent so that the results can be used over
a wide range of operating conditions. Equivalent capacitance
values are shown below.
= Fixed capacitance due to second routed array
clock (ACT 2, 1200XL, 3200DX, ACT 3 only)
= Fixed number of clock loads on the dedicated
array clock (ACT 3 only)
= Fixed number of clock loads on the dedicated
I/O clock (ACT 3 only)
CEQ Values for Actel FPGAs
CEQM
CEQI
= Equivalent capacitance of logic modules in pF
= Equivalent capacitance of input buffers in pF
1200XL
ACT 3 3200DX ACT 2 ACT 1
CEQO
= Equivalent capacitance of output buffers
in pF
Modules (CEQM
)
6.7
7.2
5.2
5.8
12.9
23.8
3.7
22.1
31.2
Input Buffers (CEQI
)
11.6
23.8
CEQCR = Equivalent capacitance of routed array clock
in pF
Output Buffers (CEQO
)
10.4
CEQCD = Equivalent capacitance of dedicated array
clock in pF
Routed Array Clock
Buffer Loads (CEQCR
Dedicated Clock Buffer
Loads (CEQCD
I/O Clock Buffer Loads
(CEQCI
)
1.6
0.7
0.9
3.5
N/A
N/A
3.9
N/A
N/A
4.6
N/A
N/A
CEQCI
= Equivalent capacitance of dedicated I/O clock
in pF
)
CL
fm
fn
= Output lead capacitance in pF
)
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piecewise linear summation
over all components that applies to all ACT 1, 1200XL,
3200DX, ACT 2, and ACT 3 devices. Since the ACT 1 family has
only one routed array clock, the terms labeled routed_Clk2,
dedicated_Clk, and IO_Clk do not apply. Similarly, the ACT 2
family has two routed array clocks, and the dedicated_Clk
and IO_Clk terms do not apply. For ACT 3 devices, all terms
will apply.
Power = VCC2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs
(p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1
+ (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2
(r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk
fp
fq1
= Average first routed array clock rate in MHz
(all families)
fq2
fs1
fs2
= Average second routed array clock rate in
MHz (ACT 2, 1200XL, 3200DX, ACT 3 only)
= Average dedicated array clock rate in MHz
(ACT 3 only)
= Average dedicated I/O clock rate in MHz
(ACT 3 only)
+
+
+
(s2 * CEQCI * fs2)IO_Clk
]
(2)
12
ACTEL [ Actel Corporation ]
