HiRel FPGAs
A32100DX Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
’–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Synchronous SRAM Operations
tRC
Read Cycle Time
8.8
8.8
4.4
11.8
11.8
5.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
tRCKHL
tRCO
tADSU
tADH
Clock High/Low Time
Data Valid After Clock High/Low
Address/Data Setup Time
Address/Data Hold Time
Read Enable Setup
Read Enable Hold
4.4
5.9
2.1
0.0
0.8
4.4
3.5
0.0
3.6
0.0
2.8
0.0
1.1
5.9
4.7
0.0
4.8
0.0
tRENSU
tRENH
tWENSU
tWENH
tBENS
tBENH
Write Enable Setup
Write Enable Hold
Block Enable Setup
Block Enable Hold
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
Read Address Valid
10.6
14.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRDADV
tADSU
tADH
11.5
2.1
0.0
0.8
4.4
3.5
0.0
15.3
2.8
0.0
1.1
5.9
4.7
0.0
Address/Data Setup Time
Address/Data Hold Time
Read Enable Setup to Address Valid
Read Enable Hold
tRENSUA
tRENHA
tWENSU
tWENH
tDOH
Write Enable Setup
Write Enable Hold
Data Out Hold Time
1.6
2.1
49
ACTEL [ Actel Corporation ]
