欢迎访问ic37.com |
会员登录 免费注册
发布采购

A1225XLV-VQC 参数 Datasheet PDF下载

A1225XLV-VQC图片预览
型号: A1225XLV-VQC
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号A1225XLV-VQC的Datasheet PDF文件第4页浏览型号A1225XLV-VQC的Datasheet PDF文件第5页浏览型号A1225XLV-VQC的Datasheet PDF文件第6页浏览型号A1225XLV-VQC的Datasheet PDF文件第7页浏览型号A1225XLV-VQC的Datasheet PDF文件第9页浏览型号A1225XLV-VQC的Datasheet PDF文件第10页浏览型号A1225XLV-VQC的Datasheet PDF文件第11页浏览型号A1225XLV-VQC的Datasheet PDF文件第12页  
Integrator Series FPGAs: 1200XL and 3200DX Families  
such as FIFOs, LIFOs, and RAM arrays. Additionally, unused  
SRAM blocks can be used to implement registers for other  
logic within the design.  
be joined together at the ends using antifuses to increase  
their lengths up to the full length of the track. All  
interconnects can be accomplished with a maximum of four  
antifuses.  
I/O Modules  
Horizontal Routing  
The I/O modules provide the interface between the device  
pins and the logic array. Figure 5 is a block diagram of the  
I/O module. A variety of user functions, determined by a  
library macro selection, can be implemented in the module  
(refer to the Macro Library Guide for more information). I/O  
modules contain a tri-state buffer, input and output latches  
which can be configured for input, output, or bi-directional  
pins (Figure 5).  
Horizontal channels are located between the rows of  
modules and are composed of several routing tracks. The  
horizontal routing tracks within the channel are divided  
into one or more segments. The minimum horizontal  
segment length is the width of a module pair, and the  
maximum horizontal segment length is the full length of the  
channel. Any segment that spans more than one-third the  
row length is considered a long horizontal segment. A  
typical channel is shown in Figure 6. Non-dedicated  
horizontal routing tracks are used to route signal nets;  
dedicated routing tracks are used for the global clock  
networks and for power and ground tie-off tracks.  
EN  
Q
D
Vertical Routing  
PAD  
From Array  
Another set of routing tracks run vertically through the  
module. Vertical tracks are of three types: input, output, and  
long, and are divided into one or more segments. Each  
segment in an input track is dedicated to the input of a  
particular module; each segment in an output track is  
dedicated to the output of a particular module. Long  
segments are uncommitted and can be assigned during  
routing. Each output segment spans four channels (two  
above and two below), except near the top and bottom of the  
array where edge effects occur. Long Vertical Tracks contain  
either one or two segments. An example of vertical routing  
tracks and segments is shown in Figure 6.  
G/CLK*  
Q
D
To Array  
G/CLK*  
* Can be Configured as a Latch or D Flip-Flop  
(Using C-Module)  
Figure 5 I/O Module  
Segmented  
Logic  
Horizontal  
Modules  
The Integrator Series devices contain flexible I/O structures  
where each output pin has a dedicated output enable  
control. The I/O module can be used to latch input and/or  
output data, providing a fast set-up time. In addition, the  
Actel Designer Series software tools can build a D-type  
flip-flop using a C-module to register input and/or output  
signals.  
Routing  
Tracks  
Antifuses  
Actel’s Designer Series development tools provide a design  
library of I/O macrofunctions which can implement all I/O  
configurations supported by the Integrator Series FPGAs.  
Vertical Routing Tracks  
Routing Structure  
Figure 6 Routing Structure  
The Integrator Series architecture uses vertical and  
horizontal routing tracks to interconnect the various logic  
and I/O modules. These routing tracks are metal  
interconnects that may either be of continuous length or  
broken into pieces called segments. Varying segment  
lengths allows interconnection of over 90% of design tracks  
to occur with only two antifuse connections. Segments can  
Antifuse Structure  
An antifuse is a “normally open” structure as opposed to the  
normally closed fuse structure used in PROMs or PALs. The  
use of antifuses to implement a programmable logic device  
results in highly-testable structures as well as efficient  
8
Discontinued – v3.0  
 复制成功!