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A1225XLV-VQC 参数 Datasheet PDF下载

A1225XLV-VQC图片预览
型号: A1225XLV-VQC
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
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Integrator Series FPGAs: 1200XL and 3200DX Families  
A3265DX Timing Characteristics  
(Worst-Case Commercial Conditions V  
= 4.75 V, T = 70°C)  
J
CC  
‘–3’ Speed  
Min. Max.  
‘–2’ Speed  
Min. Max.  
‘–1’ Speed  
Min. Max.  
‘Std’ Speed  
‘–F’ Speed  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Units  
1
Logic ModulePropagation Delays  
Combinatorial Functions  
t
Internal Array Module Delay  
2.1  
2.5  
2.4  
2.8  
2.9  
3.4  
3.7  
4.4  
3.2  
3.7  
ns  
ns  
PD  
t
Internal Decode Module Delay  
2
PDD  
Predicted Routing Delays  
tRD1  
tRD2  
tRD3  
tRD4  
tRD5  
tRDD  
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
0.3  
0.7  
0.4  
0.8  
1.2  
1.6  
3.2  
0.5  
0.5  
0.9  
0.6  
1.2  
1.8  
2.4  
4.9  
0.8  
0.5  
1.0  
1.6  
2.1  
4.1  
0.7  
ns  
ns  
ns  
ns  
ns  
ns  
1.0  
1.4  
1.4  
1.9  
2.7  
3.7  
Decode-to-Output Routing Delay  
3, 4  
0.46  
0.62  
Sequential Timing Characteristics  
tCO  
Flip-Flop Clock-to-Output  
2.3  
2.1  
2.7  
2.4  
3.1  
2.9  
4.1  
3.7  
3.5  
3.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tGO  
Latch Gate-to-Output  
tSUD  
Flip-Flop (Latch) Set-Up Time  
Flip-Flop (Latch) Hold Time  
0.35  
0.0  
0.4  
0.0  
0.47  
0.0  
0.6  
0.0  
0.5  
0.0  
tHD  
tRO  
Flip-Flop (Latch) Reset to Output  
Flip-Flop (Latch) Enable Set-Up  
Flip-Flop (Latch) Enable Hold  
Flip-Flop (Latch) Clock Active Pulse Width  
Flip-Flop (Latch) Asynchronous Pulse Width  
2.3  
2.7  
3.1  
4.1  
3.5  
tSUENA  
tHENA  
tWCLKA  
tWASYN  
0.75  
0.0  
0.9  
0.0  
4.2  
5.5  
1.0  
0.0  
4.9  
6.5  
1.3  
0.0  
6.4  
8.4  
1.1  
0.0  
5.5  
7.1  
3.7  
4.9  
Notes:  
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from  
the DirectTime Analyzer utility.  
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing  
parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts  
(adds) to the internal set-up (hold) time.  
5. VCC = 3.0V for 3.3V specifications.  
34  
Discontinued – v3.0  
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