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A1225XL-PLB 参数 Datasheet PDF下载

A1225XL-PLB图片预览
型号: A1225XL-PLB
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
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Integrator Series FPGAs: 1200XL and 3200DX Families  
A1280XL Timing Characteristics  
(Worst-Case Commercial Conditions, V  
= 4.75 V, T = 70°C)  
J
CC  
‘–3’ Speed  
Min. Max.  
‘–2’ Speed  
Min. Max.  
‘–1’ Speed  
Min. Max.  
‘Std’ Speed  
‘–F’ Speed  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Units  
1
Logic ModulePropagation Delays  
t
t
t
t
Single Module  
2.6  
2.6  
2.6  
2.6  
3.0  
3.0  
3.0  
3.0  
3.5  
3.5  
3.5  
3.5  
5.0  
5.0  
5.0  
5.0  
4.2  
4.2  
4.2  
4.2  
ns  
ns  
ns  
ns  
PD1  
CO  
GO  
RS  
Sequential Clk-to-Q  
Latch G-to-Q  
Flip-Flop (Latch) Reset-to-Q  
2
Predicted Routing Delays  
t
t
t
t
t
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
1.3  
1.8  
2.2  
2.6  
5.0  
1.4  
2.0  
2.5  
3.0  
5.7  
1.7  
2.4  
2.9  
3.5  
6.7  
2.4  
3.4  
4.1  
5.0  
9.6  
2.0  
2.9  
3.5  
4.2  
8.0  
ns  
ns  
ns  
ns  
ns  
RD1  
RD2  
RD3  
RD4  
RD8  
3,4  
Sequential Timing Characteristics  
t
t
t
t
t
t
t
t
t
t
t
f
Flip-Flop (Latch) Data Input Set-Up  
Flip-Flop (Latch) Data Input Hold  
Flip-Flop (Latch) Enable Set-Up  
Flip-Flop (Latch) Enable Hold  
Flip-Flop (Latch) Clock Active Pulse Width  
Flip-Flop (Latch) Asynchronous Pulse Width  
Flip-Flop Clock Input Period  
0.4  
0.0  
0.8  
0.0  
3.7  
3.7  
8.0  
0.0  
0.3  
0.0  
0.3  
0.4  
0.0  
0.9  
0.0  
4.3  
4.3  
8.7  
0.0  
0.4  
0.0  
0.4  
0.5  
0.0  
1.0  
0.0  
4.9  
4.9  
10.0  
0.0  
0.4  
0.0  
0.4  
0.7  
0.0  
1.4  
0.0  
7.0  
7.0  
14.0  
0.0  
0.6  
0.0  
0.6  
0.6  
0.0  
1.2  
0.0  
5.9  
5.9  
12.0  
0.0  
0.5  
0.0  
0.5  
ns  
ns  
SUD  
HD  
ns  
SUENA  
HENA  
WCLKA  
WASYN  
A
ns  
ns  
ns  
ns  
Input Buffer Latch Hold  
ns  
INH  
Input Buffer Latch Set-Up  
ns  
INSU  
OUTH  
OUTSU  
MAX  
Output Buffer Latch Hold  
ns  
Output Buffer Latch Set-Up  
ns  
Flip-Flop (Latch) Clock Frequency  
200  
167  
130  
90  
110  
MHz  
Notes:  
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual performance.  
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from  
the DirectTime Analyzer utility.  
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing  
parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts  
(adds) to the internal set-up (hold) time.  
5. VCC = 3.0V for 3.3V specifications.  
Discontinued – v3.0  
37  
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