Integrator Series FPGAs: 1200XL and 3200DX Families
A32100DX Timing Characteristics (continued)
(Worst-Case Commercial Conditions V
= 4.75 V, T = 70°C)
J
CC
3.3V ‘Std’
Speed
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter
Description
Min. Max. Min.
Max.
Min. Max. Min. Max. Min. Max. Min. Max. Units
1
TTL Output Module Timing
t
t
t
t
t
t
t
t
t
t
t
Data-to-Pad High
3.7
4.5
4.8
5.1
8.3
8.3
8.3
9.0
4.3
5.3
5.6
6.0
9.8
9.8
9.8
10.5
4.9
6.0
5.8
7.1
8.2
6.8
8.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
GLH
GHL
LSU
Data-to-Pad Low
10.1
10.7
11.4
18.5
18.5
18.5
20.1
Enable-Pad Z to High
Enable-Pad Z to Low
Enable-Pad High to Z
Enable-Pad Low to Z
G-to-Pad High
6.4
7.5
8.8
6.8
8.0
9.4
11.1
11.1
11.1
12.0
13.0
13.0
13.0
14.1
15.2
15.2
15.2
16.4
G-to-Pad Low
I/O Latch Output Set-Up
I/O Latch Output Hold
0.26
0.0
0.3
0.0
0.34
0.0
0.4
0.0
0.6
0.0
0.6
0.0
LH
LCO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
8.4
9.8
11.1
13.1
18.7
15.3
21.7
ns
t
ACO
11.8
0.03
0.04
0.04
13.8
0.037
0.05
15.7
0.04
0.06
0.05
18.5
0.05
0.07
0.06
26.5
0.07
0.10
0.09
ns
d
d
Capacitive Loading, Low to High
Capacitive Loading, High to Low
0.06 ns/pF
0.08 ns/pF
TLH
THL
t
Hard-Wired Wide-Decode Output
1
0.045
0.07
ns
WDO
CMOS Output Module Timing
t
t
t
t
t
t
t
t
t
t
t
Data-to-Pad High
Data-to-Pad Low
Enable-Pad Z to High
Enable-Pad Z to Low
Enable-Pad High to Z
Enable-Pad Low to Z
G-to-Pad High
4.5
3.7
4.8
5.1
8.3
8.3
8.3
9.0
5.3
4.3
5.6
6.0
9.8
9.8
9.8
10.5
6.0
4.9
7.1
5.8
10.1
8.2
8.3
6.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
GLH
GHL
LSU
6.4
7.5
10.7
11.4
18.5
18.5
18.5
20.0
8.8
6.8
8.0
9.4
11.1
11.1
11.1
12.0
13.0
13.0
13.0
14.1
15.2
15.2
15.2
16.4
G-to-Pad Low
I/O Latch Set-Up
I/O Latch Hold
0.26
0.0
0.3
0.0
0.3
0.0
0.4
0.0
0.6
0.0
0.6
0.0
LH
LCO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
9.9
11.0
13.2
15.5
22.3
18.2
25.6
ns
t
ACO
13.9
0.04
0.04
0.04
16.4
0.052
0.045
0.045
18.5
0.05
0.05
0.05
21.8
0.07
0.06
0.06
30.0
0.10
0.09
0.09
ns
d
d
Capacitive Loading, Low to High
Capacitive Loading, High to Low
Hard-Wired Wide-Decode Output
0.08 ns/pF
0.07 ns/pF
TLH
THL
t
0.07
ns
WDO
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
Discontinued – v3.0
43
ACTEL [ Actel Corporation ]
