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A1225XL-FVQC 参数 Datasheet PDF下载

A1225XL-FVQC图片预览
型号: A1225XL-FVQC
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号A1225XL-FVQC的Datasheet PDF文件第34页浏览型号A1225XL-FVQC的Datasheet PDF文件第35页浏览型号A1225XL-FVQC的Datasheet PDF文件第36页浏览型号A1225XL-FVQC的Datasheet PDF文件第37页浏览型号A1225XL-FVQC的Datasheet PDF文件第39页浏览型号A1225XL-FVQC的Datasheet PDF文件第40页浏览型号A1225XL-FVQC的Datasheet PDF文件第41页浏览型号A1225XL-FVQC的Datasheet PDF文件第42页  
Integrator Series FPGAs: 1200XL and 3200DX Families  
A1280XL Timing Characteristics (continued)  
(Worst-Case Commercial Conditions V  
= 4.75 V, T = 70°C)  
J
CC  
3.3V ‘Std’  
Speed  
‘–2’ Speed  
‘–1’ Speed  
‘Std’ Speed  
‘–F’ Speed  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Units  
Input Module Propagation Delays  
t
t
t
t
Pad-to-Y High  
Pad-to-Y Low  
G-to-Y High  
G-to-Y Low  
1.1  
1.3  
2.0  
2.6  
1.2  
1.4  
2.3  
3.0  
1.4  
1.7  
2.7  
3.5  
2.0  
2.4  
3.9  
5.0  
1.7  
2.0  
3.2  
4.2  
ns  
ns  
ns  
ns  
INYH  
INYL  
INGH  
INGL  
1
Input Module Predicted Routing Delays  
t
t
t
t
t
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
3.2  
3.7  
4.0  
4.6  
6.6  
3.7  
4.2  
4.5  
5.2  
7.5  
4.3  
4.9  
5.3  
6.1  
8.8  
6.1  
7.0  
5.2  
5.9  
ns  
ns  
ns  
ns  
ns  
IRD1  
IRD2  
IRD3  
IRD4  
IRD8  
7.6  
6.4  
8.7  
7.3  
12.6  
10.6  
Global Clock Network  
FO = 32  
FO = 384  
5.1  
5.7  
5.8  
6.5  
6.8  
7.6  
9.7  
10.9  
8.2  
9.1  
ns  
ns  
t
t
t
t
t
t
t
t
f
Input Low to High  
Input High to Low  
CKH  
FO = 32  
FO = 384  
5.0  
5.7  
5.7  
6.5  
6.7  
7.6  
9.6  
10.9  
8.0  
9.1  
ns  
ns  
CKL  
FO = 32  
FO = 384  
3.2  
3.5  
3.5  
3.9  
4.3  
4.6  
6.1  
6.6  
5.2  
5.5  
ns  
ns  
Minimum Pulse Width High  
Minimum Pulse Width Low  
Maximum Skew  
PWH  
PWL  
CKSW  
SUEXT  
HEXT  
P
FO = 32  
FO = 384  
3.2  
3.5  
3.5  
3.9  
4.3  
4.6  
6.1  
6.6  
5.2  
5.5  
ns  
ns  
FO = 32  
FO = 384  
0.8  
0.8  
0.9  
0.9  
1.0  
1.0  
1.4  
1.4  
1.2  
1.2  
ns  
ns  
FO = 32  
FO = 384  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
ns  
ns  
Input Latch External Set-Up  
Input Latch External Hold  
Minimum Period  
FO = 32  
FO = 384  
2.6  
3.2  
2.9  
3.7  
3.4  
4.3  
4.9  
6.1  
4.1  
5.2  
ns  
ns  
FO = 32  
FO = 384  
6.5  
7.2  
7.4  
8.0  
8.7  
9.6  
12.4  
13.7  
10.4  
11.5  
ns  
ns  
FO = 32  
FO = 384  
200  
180  
167  
150  
143  
130  
100  
90  
120  
110  
MHz  
MHz  
Maximum Frequency  
MAX  
Note:  
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual performance.  
38  
Discontinued – v3.0  
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