欢迎访问ic37.com |
会员登录 免费注册
发布采购

A1225XL-FPQC 参数 Datasheet PDF下载

A1225XL-FPQC图片预览
型号: A1225XL-FPQC
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号A1225XL-FPQC的Datasheet PDF文件第38页浏览型号A1225XL-FPQC的Datasheet PDF文件第39页浏览型号A1225XL-FPQC的Datasheet PDF文件第40页浏览型号A1225XL-FPQC的Datasheet PDF文件第41页浏览型号A1225XL-FPQC的Datasheet PDF文件第43页浏览型号A1225XL-FPQC的Datasheet PDF文件第44页浏览型号A1225XL-FPQC的Datasheet PDF文件第45页浏览型号A1225XL-FPQC的Datasheet PDF文件第46页  
Integrator Series FPGAs: 1200XL and 3200DX Families  
A32100DX Timing Characteristics (continued)  
(Worst-Case Commercial Conditions V  
= 4.75 V, T = 70°C)  
J
CC  
3.3V ‘Std’  
Speed  
‘–3’ Speed  
‘–2’ Speed  
‘–1’ Speed  
‘Std’ Speed  
‘–F’ Speed  
Parameter  
Description  
Min.  
Max.  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units  
Input Module Propagation Delays  
t
t
Input Data Pad-to-Y  
1.4  
2.9  
1.65  
3.4  
1.9  
3.8  
2.2  
4.5  
3.1  
6.4  
2.5  
5.3  
ns  
INPY  
1
INGO  
Input Latch Gate-to-Output  
ns  
ns  
ns  
1
t
t
t
Input Latch Hold  
0.0  
0.0  
0.5  
0.0  
0.6  
0.0  
0.7  
0.0  
1.0  
0.0  
INH  
INSU  
ILA  
1
Input Latch Set-Up  
0.45  
0.82  
1
Latch Active Pulse Width  
4.4  
4.8  
5.9  
6.9  
9.8  
8.1  
ns  
Input Module Predicted Routing Delays  
t
t
t
t
t
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
1.6  
2.0  
2.6  
2.6  
4.1  
1.75  
2.4  
3.0  
3.0  
4.8  
2.1  
2.7  
3.4  
3.4  
5.4  
2.5  
3.2  
4.0  
4.0  
6.4  
3.6  
4.6  
5.7  
5.7  
9.1  
2.9  
3.8  
4.7  
4.7  
7.5  
ns  
ns  
ns  
ns  
ns  
IRD1  
IRD2  
IRD3  
IRD4  
IRD8  
Global Clock Network  
t
t
t
t
t
t
t
t
f
Input Low to High  
FO=32  
FO=635  
4.7  
5.7  
5.6  
6.75  
6.3  
7.7  
7.4  
9.0  
10.5  
12.8  
8.7  
10.5  
ns  
ns  
CKH  
Input High to Low  
FO=32  
FO=635  
4.8  
6.4  
5.6  
7.5  
6.4  
8.5  
7.5  
10.0  
10.7  
14.2  
8.8  
11.7  
ns  
ns  
CKL  
Minimum Pulse Width  
High  
FO=32  
FO=635  
2.5  
2.7  
2.9  
3.2  
3.3  
3.7  
3.9  
4.3  
5.6  
6.1  
4.5  
5.0  
ns  
ns  
PWH  
PWL  
CKSW  
SUEXT  
HEXT  
P
Minimum Pulse Width  
Low  
FO=32  
FO=635  
2.5  
2.7  
2.9  
3.2  
3.3  
3.7  
3.9  
4.3  
5.5  
6.1  
4.5  
5.0  
ns  
ns  
Maximum Skew  
FO=32  
FO=635  
0.6  
0.6  
0.75  
0.75  
0.9  
0.9  
1.0  
1.0  
1.4  
1.4  
1.8  
1.8  
ns  
ns  
Input Latch External  
Set-Up  
FO=32  
FO=635  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
ns  
ns  
Input Latch External  
Hold  
FO=32  
FO=635  
2.2  
2.7  
2.5  
3.2  
2.9  
3.7  
3.4  
4.3  
4.9  
6.1  
4.0  
6.1  
ns  
ns  
Minimum Period  
(1/fmax)  
FO=32  
FO=635  
5.0  
5.5  
6.0  
6.4  
7.4  
8.2  
7.9  
8.6  
12.4  
13.7  
9.3  
10.1  
ns  
ns  
Maximum Datapath  
Frequency  
FO=32  
FO=635  
183  
167  
159  
145  
146  
133  
127  
116  
89  
81  
108  
99  
MHz  
MHz  
HMAX  
Note:  
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual performance.  
42  
Discontinued – v3.0  
 复制成功!