Integrator Series FPGAs: 1200XL and 3200DX Families
3200DX Timing Model (SRAM Functions)*
Input Delays
I/O Module
t
INPY = 1.4 ns
tIRD1 = 1.9 ns
D
Q
G
Predicted
Routing
Delays
I/O Module
DLH = 3.7 ns
tINSU = 0.45 ns
tINH = 0.05 ns
tINGO = 3.3 ns
t
RD [7:0]
RDAD [5:0]
REN
WD [7:0]
tRD1 = 1.1 ns
WRAD [5:0]
BLKEN
D
G
Q
WEN
WCLK
RCLK
tADSU = 1.5 ns
tADH = 0.0 ns
tRENSUA = 0.6 ns
t
ADSU = 1.5 ns
tADH = 0.0 ns
tGHL= 8.9 ns
LSU = 0.26 ns
tLH = 0.0 ns
t
ARRAY
CLOCKS
tWENSU = 2.6 ns
tBENS = 2.6 ns
tRCO = 3.2 ns
F
MAX = 165 MHz
*Values shown for A32200DX-3 at worst-case commercial conditions.
Discontinued – v3.0
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